Sudipta K. Ray

Ceramic mini-ball grid array package for high speed device

We have developed a Ceramic Mini Ball Grid Array (BGA) package for a high speed switch chip (200 MHz) application. In this paper, we describe the 0.5 mm pitch mini BGA package and the processes developed to fabricate this package. In addition, a matching ceramic socket that was developed to test the high speed switch chips is also briefly reviewed. The mini-BGA process enabled the packaging of the switch chip in a 21 mm ceramic substrate with 1521 solder ball connections. The main difference between the mini solder ball connections described here and conventional ceramic ball grid array (CBGA) packages is that 60/40 Pb/Sn eutectic solder is used in the mini-BGA package compared to 90/10 Pb/Sn solder balls used in CBGA packages.

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

Ceramic column grid array technology with coated solder columns

Flip-chip carriers are finding increasing use for high-performance ASIC and microprocessors chips. Many of these chips have a large I/O count and consequently drive chip carriers with high density second-level interconnection requirements (typically 400 to more than 1000). IBM has a range of Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) offerings which cover this application range. In this paper, we describe the development of a new CCGA technology with coated solder columns which allows column attach at the very end of the module assembly process. The new approach developed was to make Pb90-Sn10 solder columns with a thin barrier layer which are joined to the module I/O pads using a lead-free Sb5-Sn95 solder preforms. The barrier layer prevents the reaction of Sn/Sb with the Pb-rich column and driving the interface towards the Sn/Pb eutectic phase with its low melting point of 183/spl deg/C. As a result, during card assembly and rework of the module from the card, the column joints on the ceramic substrate do not melt. The coated CCGA structure has two beneficial attributes: being able to join to the module at the end of the module assembly (as in CBGA process), and the ability to remove the CCGA module from a card with all the columns attached to the module (like the cast CCGA structure). In this paper, the structure and attachment process of the coated CCGA and the reliability of coated CCGA connections to an organic FR-4 card are reviewed. A nonlinear finite element modeling has been carried out to study the resistance to cyclic viscoplastic deformation and related damage mechanism. A deformation-base lifetime analysis method was used for the column fatigue life prediction and was compared with the actual test data.

Flip-chip interconnection technology for advanced thermal conduction modules

Area array solder bumps on silicon devices, known as C4 balls, have been successfully used in terminating logic and memory devices to ceramic substrates in numerous IBM products over two decades. With the IBM System 390/ES9000 series of mainframe computers, this highly reliable chip termination technology has achieved improved interconnection density and total number of chip I/O connections per module. In addition, in the models 820 and 900 of ES9000 series, a novel materials set, namely glass-ceramic with Cu internal metallization along with thin-film redistribution wiring on top, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules which also have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70000 solder balls per module is discussed.<<ETX>>

Ceramic column grid array (CCGA) module for a high performance work station application

A multi-layer ceramic (MLC) substrate has been developed to package a 335 mm/sup 2/ silicon chip with a large number of transistors (15 million). The flip-chip required a package which can support a large number of I/O, and ability to cool 30 watts of power at 135 MHz. The large package pincount of 1088 led to the choice of a 42.5 mm substrate with a 1.27 mm pitch solder column grid array. In this paper, the chip and package attributes are described. A highly conductive thermal paste with a conductivity of 3.8 watt/m-deg. has been developed to provide an efficient thermal path from the flip-chip to the Al cap used on this package. Finally, the excellent reliability achieved by the column grid array connection to the second level organic card is discussed.

Device interconnection technology for advanced thermal conduction modules

The use of area array solder bumps on silicon devices known as controlled collapse chip connection (C4) balls for terminating logic and memory devices to ceramic substrates has been extended in both interconnection density and total number of chip I/O connections per module. In addition, a novel materials set, namely glass-ceramic with copper internal metallization along with thin film redistribution wiring on the top surface, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules (ATCMs). These models have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70,000 solder balls per module is discussed. >

Electrical connections to the thermal conduction modules of the IBM Enterprise System/9000 water-cooled processors

In a complex multichip carrier such as the thermal conduction module (TCM) of IBM high-performance mainframe processors, the interfaces between chips and their substrate as well as between the substrate and its printed circuit board must support a large number of electrical connections. Since chip, substrate, and board typically comprise very different materials, the electrical connections between them must be able to accommodate considerable thermally induced mechanical stress during assembly and use. This paper describes the pin attachment, chip attachment. wire bonding, and laser deletion processes used for forming the electrical connections to theglass-ceramic/copper/polyimide/copper substrate of the thermal conduction modules of the IBM Enterprise System/9000TM watercooled processors.

Engineering change (EC) technology for thin film metallurgy on polyimide films

Engineering change in multichip modules such as the IBM Thermal Conduction Module (TCM) requires making new nets on the top surface of the module. This is done either to repair opens or shorts in the internal nets or to correct design errors. Since the trend in multichip packaging in the high end is towards thin-film wiring with polyimide as the dielectric, wire-bond and laser delete processes compatible with thin-film metallurgy on polyimide films are required to carry out engineering change. The authors describe the results of a technology-development effort to optimize these processes on a metal/polyimide thin-film structure.<<ETX>>

Dual-Level Metal (DLM) method for fabricating thin film wiring structures

This paper describes a fabrication method for multilevel, thin film wiring in which each wiring level and a solid via or stud to the level below, are formed as one integral unit. The processing scheme described makes use of a photosensitive polyimide (PSPI) for defining the wiring channels and a non-photosensitive polyimide for the vias. The via opening in the non-photosensitive polyimide is formed by laser ablation while the wiring channels are formed in the PSPI layer by photolithography. The via hole and the channels in the PSPI are filled in the same metallization step consisting of electroplating copper over a sputtered seed layer. The wiring pattern is finally delineated when a planarization step removes the excess plated copper. This processing method, which we refer to as the Dual Layer Metallization (DLM) method, is found to be very economical, in terms of the number of process steps involved, for forming multilevel, polyimide-copper wiring structures.<<ETX>>

Qualification of low-k 90nm technology dies with Pb-free bumps on a build-up laminate package (PBGA) with Pb-free assembly processes

Flip-chip packages have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic ball grid array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines with exemptions allowed for server and other networking hardware. Towards this goal, IBM has been actively developing and qualifying Pb-free and Pb-reduced packages that cover the range of advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm wafers also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thin-core (400 micron) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90 nm devices with Amkor developed Pb-free bumps using large die and build-up laminates. The die size used is ~15mm and the laminate qualified is 42.5mm with 1mm pitch Pb-free BGA. The bump pitch is 200micron. In this paper, we summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 90nm technology on thin-core build-up laminates. Optimizations required for underfill material compatible with Pb-free bumps and low-k die are reviewed. Finally, high speed devices generate a significant amount of power, and an optimum thermal solution for FC-PBGA package is essential. Summary of package-level thermal performance is presented