Keith W. Tang

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

170-GHz transceiver with on-chip antennas in SiGe technology

A single-chip transceiver with on-die transmit and receive antennas, Rx and Tx amplifiers, 165-GHz oscillator and static frequency divider is reported in a SiGe HBT process with fT/fMAX of 270 GHz/340 GHz. This marks the highest frequency transceiver in silicon and the highest level of functional integration above 100 GHz in any semiconductor technology. The downconversion gain peaks at -5 dB and the transmit power is -5 dBm when measured at the transceiver pads. Both degrade by approximately 25 dB when measured above the antennas of the transceiver with on-die antennas. The experimental performance of dipole (with and without floating metal strips) and patch antennas is also investigated. The measured 15-dB gain of a standalone amplifier is centered at 170 GHz and remains higher than 10 dB from 160 GHz to 180 GHz while the saturated output power is 0 dBm at 165 GHz.

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

Design and Scaling of W-Band SiGe BiCMOS VCOs

This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors. Based on a study of the optimal biasing conditions for minimum phase noise, it is shown that VCOs can be used to monitor the mm-wave noise performance of SiGe HBTs. Measurements show a 106 GHz VCO operating from 2.5 V with phase noise of -101.3 dBc/Hz at 1 MHz offset, which delivers +2.5 dBm of differential output power at 25degC, with operation verified up to 125degC. A BiCMOS VCO with a differential MOS-HBT cascode output buffer using 130 nm MOSFETs delivers +10.5 dBm of output power at 87 GHz.

Frequency Scaling and Topology Comparison of Millimeter-wave CMOS VCOs

This paper presents an algorithmic design methodology and frequency scaling technique for CMOS VCOs. It illustrates the almost ideal scaling of a fundamental 10-GHz, 90-nm CMOS Colpitts VCO with -117 dBc/Hz phase noise and 4 dBm output power to 77 GHz. The 77-GHz VCO features linear 8.3% tuning range and a phase noise of -100.3 dBc/Hz at 1 MHz offset. The first complementary cross-coupled VCO operating at 77 GHz is also reported. In addition, a new figure of merit for CMOS VCO based on the one defined in the 2003 ITRS is proposed to adequately account for the VCO output power and efficiency

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples

This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.

65-nm CMOS, W-Band Receivers for Imaging Applications

Two 76-92 GHz receivers, featuring 3-stage cascode LNAs coupled through a transformer to a double-balanced Gilbert-cell mixer and differential DC-5GHz IF buffer, are reported in 65-nm general purpose (GP) CMOS technology. One receiver features a traditional LNA with series-series inductive feedback, while the LNA of the second receiver employs a shunt-series, transformer-feedback cascode stage. Both receivers have a differential down-conversion gain of 12 dB, an input P1dB of -13 dBm, and a double-sideband noise figure of 9-10 dB. They each occupy an area of 550 mum times 550 mum and consume 94 mW. An LO-to-RF isolation of 60 to 59 dB was measured for LO signals in the 80-85 GHz range. The transformer-feedback provides a broader bandwidth input match, lower than -10 dB from 74 to 95 GHz.

The Invariance of the Noise Impedance in n-MOSFETs across Technology Nodes and its Application to the Algorithmic Design of Tuned Low Noise Amplifiers

The measured noise impedance of MOSFETs is found to be invariant across technology nodes. Together with the invariance of the optimum noise figure current density, JOPT, this allows for optimally noise matched LNAs to be ported without redesign between technology nodes and for a given design to be scaled in frequency. The design porting and frequency scaling are validated experimentally on record low noise LNAs fabricated in 90 nm and 130 nm CMOS technology

160 GHz On-Chip Dipole Antenna Structure in Silicon Technology

This paper presents the electromagnetic modelling and design of a on-chip dipole antenna operating in the 160 GHz frequency range. The antenna is fabricated in the 130 nm SiGe HBT with BiCMOS9 backend technologies. The near field measurements are in good agreement with the electromagnetic simulation results obtain using a appropriate model.