Mehdi Khanpour

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

W-band 65-nm CMOS and SiGe BiCMOS transmitter and receiver with lumped I-Q phase shifters

This paper describes 80–94 GHz and 70–77 GHz I-Q phase shifters and the corresponding transmitter and receiver ICs, fabricated in 65-nm CMOS and SiGe BiCMOS technologies, respectively. Lumped inductors and transformers are employed to realize small-form factor 90° hybrids as needed in high density phased arrays. The CMOS transmitter operates with a saturated output power of +3 dBm and exhibits maximum absolute phase and amplitude errors of 14° and 5.5 dB, respectively, when the phase is varied from 0° to 360° in steps of 22.5°. The absolute phase error in the SiGe BiCMOS receiver is less than 8°, with a maximum gain imbalance below 3 dB over its 3-dB bandwidth of 70–77 GHz. The peak gain and power consumption are 3.8 dB and 142 mW from 1.2V supply for the CMOS transmitter, and 17 dB and 128 mW from 1.5V and 2.5V supplies for the SiGe BiCMOS receiver.

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples

This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.

65-nm CMOS, W-Band Receivers for Imaging Applications

Two 76-92 GHz receivers, featuring 3-stage cascode LNAs coupled through a transformer to a double-balanced Gilbert-cell mixer and differential DC-5GHz IF buffer, are reported in 65-nm general purpose (GP) CMOS technology. One receiver features a traditional LNA with series-series inductive feedback, while the LNA of the second receiver employs a shunt-series, transformer-feedback cascode stage. Both receivers have a differential down-conversion gain of 12 dB, an input P1dB of -13 dBm, and a double-sideband noise figure of 9-10 dB. They each occupy an area of 550 mum times 550 mum and consume 94 mW. An LO-to-RF isolation of 60 to 59 dB was measured for LO signals in the 80-85 GHz range. The transformer-feedback provides a broader bandwidth input match, lower than -10 dB from 74 to 95 GHz.

On-die source-pull for the characterization of the W-band noise performance of 65 nm general purpose (GP) and low power (LP) n-MOSFETs

A low-loss source-pull tuner network consisting of transmission lines and CMOS switches is integrated on the same chip with a W-band LNA in 65nm RF CMOS technology, allowing for the accurate characterization of the optimal noise impedance of n-MOSFETs in the W-band. In a separate experiment, a W-band downconverter is integrated along with GP and LP transistors to resolve the difference in noise figures of GP and LP MOSFETs fabricated on the same die. These measurements show that, in the same technology node, GP n-MOSFETs exhibit 1dB lower NF50 than LP devices. Experimental evidence is provided for the first time that the optimum noise figure current density depends linearly on the lateral electric field in the channel, but invariant between GP and LP transistors. Based on the characterized MOSFET noise parameters, GP CMOS LNAs with 6dB and 7dB noise figures were designed and tested at 75–85 GHz and at 80–100 GHz, respectively. These LNAs exhibit 2–3 dB lower noise figure than an equivalent CMOS LNA fabricated in a 65nm RF LP CMOS process.

A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm Psat.

CMOS receivers in the 100–140 GHz range

This paper reviews recent research conducted at the University of Toronto on the development of imaging and radio transceivers in CMOS, aimed at operation in the 100-GHz to 200-GHz range. Two receivers fabricated in 65-nm GPLP CMOS technology are described. The first is a 90–100 GHz IQ receiver with 7-dB noise figure, 10.5-dB downconversion gain and fundamental frequency VCO. The second receiver has a double-sideband architecture and operates in the 135–145 GHz range and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer and a dipole antenna.

Design and Modeling Considerations for Fully-Integrated Silicon W-Band Transceivers

This paper presents circuit design methodologies, modeling techniques, and circuit architectures for silicon transceivers above 77 GHz. The architectures of three existing CMOS and SiGe BiCMOS receivers and transceivers are compared to demonstrate the variety of choices available to the circuit designer, and to highlight design challenges that arise in transceivers above 77 GHz. A comparison of 65 nm CMOS and 130 nm SiGe BiCMOS circuits illustrates the suitability of both technologies in W-Band systems. Inductor and transformer scaling is demonstrated beyond 160 GHz, and the extension of an existing modeling technique for inductors is shown to accurately model transformers and transmission lines. The optimum biasing of power amplifiers is investigated in CMOS and SiGe HBT technologies.