Kejia Wang

Thermally evaporated Cu2ZnSnS4 solar cells

High efficiency Cu2ZnSnS4 solar cells have been fabricated on glass substrates by thermal evaporation of Cu, Zn, Sn, and S. Solar cells with up to 6.8% efficiency were obtained with absorber layer thicknesses less than 1 μm and annealing times in the minutes. Detailed electrical analysis of the devices indicate that the performance of the devices is limited by high series resistance, a “double diode” behavior of the current voltage characteristics, and an open circuit voltage that is limited by a carrier recombination process with an activation energy below the band gap of the material.

Structural and elemental characterization of high efficiency Cu2ZnSnS4 solar cells

We have carried out detailed microstructural studies of phase separation and grain boundary composition in Cu2ZnSnS4 based solar cells. The absorber layer was fabricated by thermal evaporation followed by post high temperature annealing on hot plate. We show that inter-reactions between the bottom molybdenum and the Cu2ZnSnS4, besides triggering the formation of interfacial MoSx, results in the out-diffusion of Cu from the Cu2ZnSnS4 layer. Phase separation of Cu2ZnSnS4 into ZnS and a Cu–Sn–S compound is observed at the molybdenum-Cu2ZnSnS4 interface, perhaps as a result of the compositional out-diffusion. Additionally, grain boundaries within the thermally evaporated absorber layer are found to be either Cu-rich or at the expected bulk composition. Such interfacial compound formation and grain boundary chemistry likely contributes to the lower than expected open circuit voltages observed for the Cu2ZnSnS4 devices.

High efficiency Cu 2 ZnSn(S x Se 1−x ) 4 thin film solar cells by thermal co-evaporation

We report on the device results of thermally evaporated high efficiency Cu2ZnSn(SxSe1−x)4 (CZTSSe) thin film solar cells with power conversion efficiencies of 7.1% (x=1.0) and 7.5% (x=0.34). We have carried out extensive electrical and structural characterization of CZTSSe solar cells to identify major factors that limit the efficiency. Bias-dependent quantum efficiency measurements revealed ineffective collection of charge carriers photo-generated deep in the absorber layer suggesting a short minority carrier diffusion length, which was confirmed by time-resolved photoluminescence measurements. Temperature-dependence of the series resistance of the devices is consistent with the presence of a Schottky-type barrier in the back contact, likely caused by secondary phases near the CZTS/Mo interface and/or an interfacial MoSx layer.

Wire-textured silicon solar cells

Wire array or nanowire based silicon solar cells based upon radial p-n junctions have been investigated over the past few years for enhanced light trapping, as well as for being able to offer radial junctions that are in close proximity to photogenerated carriers. To date, however, silicon wire array cells have not been able to demonstrate efficiencies higher than their planar controls. We have studied of wire textured solar cells using two approaches. The first experiment focuses on single crystal Si substrate. We use thin (2.3 µm) p- (∼5°1015 /cm3) epitaxial Si/p+(∼5°1019 /cm3) Si(100) substrates to fabricate wire arrays using a simple, top down process employing a self assembled mask of close packed polystyrene micro-spheres. The effective absorber depth is confined to the thin p- layer since the photocurrent generation in the p+ layer is negligible due to low minority carrier lifetimes. The thin layer accentuates the effect of the wire structures. Through a detailed study of wire diameter and conformality, we demonstrate wire array devices that outperform the planar controls in terms of efficiency and photocurrent. The second experiment focuses on multicrystalline Si. We show that the self assembled monolayer mask process can be adapted for wire texturing multicrystalline Si solar cells successfully in a low cost, scalable process using chemical functionalization as a result of which a simple dispensing technique can be used without the need for spinning or squeegee based approaches. We demonstrate cells with 20% higher short circuit current than the planar control, and show that the wire textured samples have a higher “pseudo”-efficiency when the series resistance effects are excluded. Finally, through an extensive examination of the electrical performance of the cells using both thin single crystal, as well as multi-crystalline bulk Si absorber layers, we have identified the key issues of light trapping, internal quantum efficiencies and series resistance as a function of wire diameter.