Kenji Miyanaga

A 60GHz wireless transceiver employing hybrid analog/digital beamforming with interference suppression for multiuser gigabit/s radio access

This paper presents a 60GHz analog/digital beamforming transceiver that effectively suppresses interference signals, targeting WiGig/IEEE 802.11ad standard. A prototype has been built with 40nm CMOS analog front-ends as well as offline baseband digital signal processing. Measurement shows 3.1dB EVM advantage over the conventional two-stream diversity during a packet collision situation.

A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad

A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.

VCO gain nonlinearity calibration with frequency offset/drift compensation for 3G/GSM/EDGE polar modulation transmitter

In recent 3G cellular handset, small-sized RF is strongly demanded. Polar modulation is one of the candidates to eliminate peripheral RF components. To apply polar modulation for wideband application, high linearity of phase modulator is required. In this paper, VCO gain nonlinearity calibration for phase modulator is proposed. The proposed procedure can calibrate the nonlinearity including frequency offset and frequency drift, which have an impact on EVM performances. Simulation and measurement results show the proposal can achieve excellent EVM of 5.8%.

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A 60 GHz phase-locked loop (PLL) synthesizer with an injection locked frequency divider (ILFD) is presented. The PLL employs a simple and fast calibration algorithm consisting of the VCO sub-band selection and the adjustment of the ILFD locking range. The proposed PLL is demonstrated using 90 nm CMOS. The calibration process converges within 100 μsec at all 4-channels defined by the Wireless Gigabit Alliance (WiGig).