Koji Takinami

Millimeter-Wave Evolution for 5G Cellular Networks

Triggered by the explosion of mobile traffic, 5G (5th Generation) cellular network requires evolution to increase the system rate 1000 times higher than the current systems in 10 years. Motivated by this common problem, there are several studies to integrate mm-wave access into current cellular networks as multi-band heterogeneous networks to exploit the ultra-wideband aspect of the mm-wave band. The authors of this paper have proposed comprehensive architecture of cellular networks with mm-wave access, where mm-wave small cell basestations and a conventional macro basestation are connected to Centralized-RAN (C-RAN) to effectively operate the system by enabling power efficient seamless handover as well as centralized resource control including dynamic cell structuring to match the limited coverage of mm-wave access with high traffic user locations via user-plane/control-plane splitting. In this paper, to prove the effectiveness of the proposed 5G cellular networks with mm-wave access, system level simulation is conducted by introducing an expected future traffic model, a measurement based mm-wave propagation model, and a centralized cell association algorithm by exploiting the C-RAN architecture. The numerical results show the effectiveness of the proposed network to realize 1000 times higher system rate than the current network in 10 years which is not achieved by the small cells using commonly considered 3.5 GHz band. Furthermore, the paper also gives latest status of mm-wave devices and regulations to show the feasibility of using mm-wave in the 5G systems.

An Outphasing Power Amplifier for a Software-Defined Radio Transmitter

A software-defined radio (SDR) transmitter needs a universal modulator and power amplifier to support any modulation in any band. There is a simple solution, namely, a Cartesian I-Q upconverter followed by a linear power amplifier, but for complex modulations its power conversion efficiency is often under 10%. Therefore, the search continues for a more efficient solution. One possibility is to harness the high efficiency of a saturated power amplifier but somehow make it deliver amplitude-modulated waveforms. Polar modulation has found use in enabling EDGE on GSM handsets, but we believe outphasing, or linear amplification using nonlinear components (LINC), offers a more enduring solution for a broader class of modulations.

Phase-Noise Analysis in Rotary Traveling-Wave Oscillators Using Simple Physical Model

We show that the rotary traveling wave oscillator (RTWO) is well treated as a superposition of multiple standing-wave oscillators (SWOs). Based on the proposed physical interpretation, we derive a phase-noise formula for the SWO, and extend it to the RTWO, which can predict thermally induced phase noise with no more complexity than the well-understood LC voltage-controlled oscillator. Measurement and simulation validate the analysis. The physically based approach and simple resulting expressions make it possible to design the RTWO for a given phase noise without lengthy simulations.

A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the digital domain. Unlike the conventional time-to-digital converter (TDC) approach, it eliminates power hungry inverter delay chains as well as real time period normalization. The proposed approach significantly simplifies the ADPLL architecture while maintaining excellent phase noise. The PLL is implemented in a 65 nm CMOS process. The 32-phase embedded phase-to-digital converter (PDC) achieves 2π/64 phase resolution. The measured in-band phase noise is -108 dBc/Hz at 4 GHz with a 78 MHz reference and a 1 MHz loop bandwidth.

Phase Error Calibration Technique for Rotary Traveling Wave Oscillators

Phase error calibration technique that is suitable for an RTWO is presented. By introducing non-uniform capacitors in the distributed resonator, the phase relationships among multiphase outputs available from the RTWO are adjusted to compensate for physical asymmetries. To have a better understanding of the proposed method, we develop a model in which the RTWO is described as injection locked multiple SWOs. The proposed model reveals possible modes of oscillation, their stability, and provides better design insight. The prototype is fabricated in a 110 nm RF-CMOS process, demonstrating more than 10° phase control range at the vicinity of 3 GHz oscillation frequency.

A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS

All-digital phase-locked loops (ADPLLs) have recently become more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been tremendous efforts to improve TDC performance, i.e., maximizing resolution and reducing power consumption, but they normally require additional complex circuits.

A 60GHz wireless transceiver employing hybrid analog/digital beamforming with interference suppression for multiuser gigabit/s radio access

This paper presents a 60GHz analog/digital beamforming transceiver that effectively suppresses interference signals, targeting WiGig/IEEE 802.11ad standard. A prototype has been built with 40nm CMOS analog front-ends as well as offline baseband digital signal processing. Measurement shows 3.1dB EVM advantage over the conventional two-stream diversity during a packet collision situation.

Millimeter wave CMOS integrated circuit for multi-gigabit communication and radar applications

Millimeter wave band is suitable for high-speed communication and high-precision sensing applications by its broadband characteristics. The key factor for these applications is to realize wireless systems that can be practically integrated by using complementary metal-oxide semiconductor (CMOS) technology. In millimeter wave bands, precise circuit models and digital calibration techniques for correcting variations of CMOS analog circuits are required for commercialization. This paper describes 60 GHz and 79 GHz CMOS chipsets for multi-gigabit wireless communications and phased-array radar applications. Additionally it introduces 140 GHz CMOS integrated circuit design as future challenges toward Terahertz era.

A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad

A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.

A Novel Parasitic-Aware Synthesis and Verification Flow for RFIC Design

The design of radio-frequency integrated circuits (RFICs) is highly sensitive to layout parasitics. In conventional methodologies, the layout parasitics are known only after the layout is complete and the schematic is resized to compensate for these parasitics. The drawback of such a methodology is that the convergence of this design iteration remains unpredictable. This paper proposes a novel synthesis and verification flow for RFIC designs. The design flow is composed of three stages: circuit sizing with floorplan, performance-aware floorplan refinement, and full-wave electromagnetic (EM) extraction. Layout parasitics are considered throughout the design flow in the proposed methodology. As a result, parasitic closure can be achieved quickly and design iterations may not be required. As an example, the proposed design flow is applied to a cross-coupled inductance-capacitance (LC) VCO. Demonstrating the efficiency of the proposed flow for RFIC designs, it required only two weeks to meet all the design specifications with no iterations