Kenji Sakaue

A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture

The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated. >

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells, dual-port cells, and CAM cells into a memory array to improve silicon area efficiency. The cache macro exhibits 9-ns typical clock-to-HIT delay as a result of several circuit techniques, such as a section word-line selector, a dual transfer gate, and 1.0- mu m CMOS technology. It supports multitask operation with logical addressing by a selective clear circuit. The RISC includes a double-word load/store instruction using a 64-b bus to fully utilize the on-chip cache macro. A test scheme allows measurement of the internal signal delay. The test device design is based on the unified design rules scalable through multigenerations of process technologies down to 0.8 mu m. >

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8- mu m BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical). >