Kenneth D. Pedrotti

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/¿(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ¿A switch control ramp current from a 2.5 V supply.

A Patch-Clamp ASIC for Nanopore-Based DNA Analysis

In this paper, a fully integrated high-sensitivity patch-clamp system is proposed for single-molecule deoxyribonucleic acid (DNA) analysis using a nanopore sensor. This system is composed of two main blocks for amplification and compensation. The amplification block is composed of three stages: 1) a headstage, 2) a voltage-gain difference amplifier, and 3) a track-and-hold circuit, that amplify a minute ionic current variation sensed by the nanopore while the compensation block avoids the headstage saturation caused by the input parasitic capacitances during sensing. By employing design techniques novel for this application, such as an instrumentation-amplifier topology and a compensation switch, we minimize the deleterious effects of the input-offset voltage and the input parasitic capacitances while attaining hardware simplicity. This system is fabricated in a 0.35 μm 4M2P CMOS process and is demonstrated using an α-hemolysin protein nanopore for detection of individual molecules of single-stranded DNA that pass through the 1.5 nm-diameter pore. In future work, the refined system will functionalize single and multiple solid-state nanopores formed in integrated microfluidic devices for advanced DNA analysis, in scientific and diagnostic applications.

HBT transmitter and data regenerator arrays for WDM optical communications application

Current research on next generation Wavelength Division Multiplexed (WDM) all optical networks has identified the need for arrays of laser driver circuits and arrays of receivers, clock recovery, and decision circuits. This paper reports on the development of two AlGaAs-GaAs HBT-based circuits: an eight-channel laser driver array and four-channel signal regeneration array including the limiting amplifier, clock recovery, and decision functions one intended for operation at 155 Mb/s. Subcircuits of the clock recovery array have been verified as suitable for use up to 2.488 Gb/s. >

A 10-Gb/s high-isolation, 16/spl times/16 crosspoint switch implemented with AlGaAs/GaAs HBT's

A high-isolation, 16/spl times/16 crosspoint switch is reported, capable of aggregate data throughput of 160 Gb/s with low crosstalk and output jitter. Each of the 16 fully asynchronous channels can transmit data at rates up to 10 Gb/s with a worst case r.m.s. output jitter of 4 ps. Single channel operation output jitter below 2.8 ps r.m.s. has been demonstrated. The high-isolation circuitry allows for inter-channel crosstalk isolation of more than 40 dB with all channels operative. The circuit is based on AlGaAs/GaAs heterojunction bipolar transistor technology.

Optoelectronic Integrated Circuits For High Speed Signal Processing

Advances in computational speed and system complexity are pro-ceeding at a rapid pace. As systems become more complex and demands for computation speed increase, parallel processing becomes the solution to meet-ing the requirements for future systems. A significant bottleneck in these and other systems is interconnect and communication problems between chips and subsystems. In addition, communication systems designers need rugged and reliable high speed transmitters and receivers. This paper discusses the design, development, and performance of GaAs optoelectronic integrated circuits for application in optical interconnection control and signal processing. We review the requirements and approaches for realization of practical optical intercon-nects and report on work in progress at Rockwell. Performance and design criteria of optical transmitters and receivers as well as data obtained on 1:8 demultiplexed receivers are given.

An integrated patch-clamp amplifier for ultra-low current measurement on solid-state nanopore

In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pARMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm2. This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.

Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8 dB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm2 in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.

Rotary Traveling-Wave Oscillators, Analysis and Simulation

Rotary traveling-wave oscillators (RTWOs) are a new transmission-line based approach to gigahertz rate oscillators. This paper presents the fundamental theory of RTWOs in both the weakly nonlinear and strongly nonlinear regions of operation, including their multimode characteristics, quality factor, nonlinearity, and edge rate of the oscillating waveform. Finally we use the theory to derive analytic expressions for thermally induced phase noise. Our theoretical results are then compared with accurate simulations.

HBT devices and circuits for signal and data processing

Abstract Production and laboratory AlGaAs/GaAs HBT processes were developed, enabling implementation of high-precision and high-speed circuits to meet the ever increasing demands on information bandwidths. Under normal bias conditions, the production HBT process shows transistor f t and f max above 50 GHz, while the laboratory process reveals f t of 60 GHz and f max of 110 GHz. With these two HBT processes, numerous high-speed and high-precision circuits for signal and data processing were implemented. In particular, we have designed and fabricated a 8-bit, 2 GS s −1 ADC and a 6-bit, 4 GS s −1 ADC for instrumentation and digital receiver applications; a 40 GBit s −1 4:1 multiplexer and an 8-channel, 2.5 GBit s −1 laser driver array for optical communication transmitters; a 50 dBΩ, 25 GHz preamplifier, a DC-26 GHz 10–16 dB variable gain amplifer, a 30 GBit s −1 data/clock regeneration circuit, two 40 GBit s −1 nonlinear (differentiate/rectify and delay/multiply) clock regeneration circuits, and a 40 GBit s −1 phase detector circuit for optical communication receivers.

HIGH SPEED CIRCUITS FOR LIGHTWAVE COMMUNICATIONS

Recent increase in the demand for bandwidth in the telecommunications network has stimulated both research and commercial activity in high-speed electronics. This paper summarizes the technical issues that bear on high-speed circuits in this context, as well as the device technologies available for these circuits in both laboratory and commercial processes. Finally a tutorial treatment is given of the main design requirements pertinent to circuits required for lightwave systems.