Kenneth D. Wagner

Design for testability of mixed signal integrated circuits

A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integration. The proposed test methodology consists of (1) establishing the digital test model for testing of digital logic and (2) establishing the analog test mode and each of the submodes (called test configurations) for serial or parallel testing of analog partitions. Digital and analog circuitry must be isolated from each other, i.e. an uncontrolled analog signal must not be able to affect the digital test mode and vice versa.<<ETX>>

Clock system design

Provides a framework for understanding system timing and then describes how the computer clock system executes the timing specifications. He examines clock generation and the construction of clock-distribution networks, which are integral to any clock system. Examples from contemporary high-speed systems highlight several common methods of clock generation, distribution, and tuning. Tight control of system clock skew is stressed.<<ETX>>

Design for testability of analog/digital networks

The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans. >

ENHANCING BOARD FUNCTIONAL SELF-TEST BY CONCURRENT SAMPLING

Board test using functioiial self-test code can be augmented by concurrently sampling signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. This is a general method to enhance board test and diagnosis, po1,erXtidy adding every chip J/O pin as an observation point that is observed frequently and coupled to the self-test. Tests continue to execute at the normal board operating speed. This combination of fnnctional and strudural testing offers improved effectiveness over functional testing alone.