Kenneth Rose

Fabrication and Performance Limits of Sub-0.1 µm Cu Interconnects

As the on-chip interconnect linewidth and film thickness shrink below 0.1 µm, the size effect on Cu resistivity becomes important, and the electrical performance deliverable by such narrow metal lines needs to be assessed critically. From the fabrication viewpoint, it is also crucial to determine how structural parameters affect resistivity in the sub-0.1 µm feature size regime. To evaluate the scaling of resistivity with thickness, we have fabricated a series of Ta/Cu/Ta/SiO 2 thin film structures with Cu thickness ranging from 1 µm to 0.02 µm. These test structures revealed a far larger (∼2.3 ×) size effect than that expected from surface scattering. We have also fabricated test structures containing 50-nm-wide Cu lines wrapped in Ta-based liners and embedded in insulating SiO 2 using e-beam lithography, high-density plasma etching, ionized PVD Cu deposition, and chemical-mechanical planarization processes. Direct current (16 nA) resistance measurements from these 50-nm-wide Cu lines have also shown a higher- than-expected distribution of resistivity. Cross-sectional TEM and surface AFM observations suggest that the observed extra resistivity increase can be attributed to small grain sizes in ultra- thin Cu films and to Cu/Ta interface roughness. Monte Carlo simulations are used to quantify the extra resistivity resulting from interface roughness.

The trials of wafer-scale integration: Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it fly

The advantages and problems of wafer-scale integration (WSI) are described. The advantages of semiconductor integrated circuits are high reliability, minimized interconnections, and decreased signal delay. The problems concern heat removal, signal quality, and the need for discretionary wiring. Finally, some recent approaches to WSI fabrication are discussed.

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.

3D DRAM Design and Application to 3D Multicore Systems

From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.

First-order performance prediction of cache memory with wafer-level 3D integration

The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a high density of high-performance, low-parasitic vertical interconnects. A wafer-level 3D design is partitionable into multiple chips connected by short vertical vias. This arrangement reduces the length of many global interconnects without introducing any logic complexity. Wafer-level 3D integration also reduces the required number of repeaters, thereby improving the area efficiency and reducing the power consumed within the interconnect network. With micron-size interwafer vias, wafer-level 3D integration allows a large memory bandwidth with little wafer area consumption. We have developed a software program that allows a first-order comparison of cache designs in 2D and 3D IC technologies. We present a first-order estimate of the performance improvements achieved by 3D implementation of cache memory, with emphasis on large caches in deep-submicron technologies.

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

This paper discusses through-strata-vias (TSVs) technology and presents modeling results of their electrical performance using Agilents ADS and Momentum simulator. Since TSV is an essential component in three-dimensional (3D) integration/packaging, it is important to explore and investigate its electrical characteristics. A simple face-to-back TSV is studied in frequency domain and time domain. The impact of physical configurations and materials on TSV electrical characteristics is evaluated. An equivalent circuit model is proposed, and the values of passive elements (resistance, inductance and capacitance) within the model are extracted from full-wave scattering parameters.

Ge diffusion at Ge/GaAs heterojunctions

Interdiffusions at Ge/GaAs heterojunctions formed by the epitaxial deposition of Ge films on GaAs have been studied for temperatures ranging from 650–800 °C. The diffusion coefficients of Ge in GaAs have been found to be 1.6×10−5 exp(−2.06/kT) for Cr: and Si:doped GaAs. After the diffusion heat treatment, Ge was found to be p type and ohmic.

Low‐temperature sintered AuGe/GaAs ohmic contact

Ohmic contacts with low specific‐contact resistivity and with contact morphology superior to conventionally alloyed contacts have been made to n‐type GaAs by sintering AuGe films on GaAs at 315 and 330 °C for several hours. The specific contact resistivities were found to decrease with sintering time and values as low as 3×10−6 Ω cm2 were obtained for contacts on GaAs (doped with silicon to a concentration of 1018 cm−3) after sintering at 330 °C for 1 h. Secondary Ion Mass Spectrometry profiling of the sintered films has been used to show that the ohmic contact formation is due to an enhanced diffusion of Ge into GaAs.

Modeling microprocessor performance

Preface. 1. Introduction. 2. System Level Representation. 3. Interconnect Parameters. 4. Transistor Count and Area Models. 5. System Wireability. 6. Device Parameters. 7. Cycle Time Estimation Model. 8. System Power Dissipation. 9. Microprocessor Performance Evaluation. Index.

Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network

Through-strata-via (TSV) is regarded as a critical component in 3D integration that extends Moores Law. This paper reports on TSV crosstalk performance under high speed operations using a 3D electromagnetic field solver and a SPICE simulator in both the frequency domain and time domain. Impacts of the rise time, the TSV pitch/height, the substrate resistivity and the guarding TSV termination on crosstalk noise are studied. Effects of adjacent aggressors and their switching patterns on time delay and peak noise of the victim TSV signal are evaluated. For large and dense TSV networks, crosstalk matrices of different TSV line/array arrangements are investigated at certain frequency points, detailing the coupling noise levels among these TSVs. Furthermore, the frequency dependent near-end crosstalk (NEXT) and far-end crosstalk (FEXT) are accurately modeled by SPICE tools.