Siddharth Devarajan

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.

Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs

A 3D IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer vias and compatibility of the process steps with 130 nm CMOS SOI devices and circuits indicate the viability of the process flow. Memory-intensive digital processors with large L2 caches have shorter access time and cycle time with 3D implementations. Performance advantages of recently designed SiGe BiCMOS pipelined A/D converters have promising figure-of-merits and illustrate partitioning issues for silicon RF ICs. Comparison with system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

Fully Monolithic Cellular Buck Converter Design for 3-D Power Delivery

A fully monolithic interleaved buck dc-dc point-of-load (PoL) converter has been designed and fabricated in a 0.18-mm SiGe BiCMOS process. Target application of the design is 3-D power delivery for future microprocessors, in which the PoL converter will be vertically integrated with the processor using wafer-level 3-D interconnect technologies. Advantages of 3-D power delivery over conventional discrete voltage regulator modules (VRMs) are discussed. The prototype design, using two interleaved buck converter cells each operating at 200 MHz switching frequency and delivering 500 mA output current, is discussed with a focus on the converter power stage and control loop to highlight the tradeoffs unique to such high-frequency, monolithic designs. Measured steady-state and dynamic responses of the fabricated prototype are presented to demonstrate the ability of such monolithic converters to meet the power delivery requirements of future processors.

Multilevel flash memory on-chip error correction based on trellis coded modulation

This paper presents a multilevel (ML) flash memory on-chip error correction system design based on the concept of trellis coded modulation (TCM). This is motivated by the non-trivial modulation process in ML memory storage and the effectiveness of TCM on integrating coding with modulation to provide better performance. Using code storage 2bits/cell flash memory as a test vehicle, the effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost, and operation latency, has been successfully demonstrated

Die-on-wafer and wafer-level 3D integration for millimeter-wave smart antenna transceivers

A three-dimensional (3D) IC technology platform for high-performance, heterogeneous integration of silicon ICs for mm-wave smart antenna transceivers is presented. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. A low noise amplifier (LNA), power amplifier (PA), and an analog-to-digital converter (ADC) are designed in RF-enhanced SiGe BiCMOS process to operate in the 24 GHz ISM band These critical design blocks serve as a step towards the realization of a complete system integrated with I/O matching networks, switches, antennas, and digital processing in a 3D configuration

A 87 dB, 2.3 GHz, SiGe BiCMOS operational transconductance amplifier

This paper describes a 3.3 V, fully differential SiGe BiCMOS operational transconductance amplifier (OTA) for switched capacitor applications. The simulated DC gain of the OTA is 87 dB and its unity gain frequency is 2.3 GHz at a phase margin of 63 degrees. The OTA is optimally compensated for fast settling using a 0.6 pF capacitor, dissipates 17 mW power, has a differential output swing of 2.4 V and the differential input-referred noise PSD is 2.7 nV//spl radic/Hz. This OTA settles to 0.01% accuracy within 4.3 ns when configured in a closed loop with feedback factor /spl beta/ = 1/2 . The above specifications will allow realization of a 12-bit, 115 MS/s gain-of-2 sample and hold amplifier for use at the front end of a pipeline ADC. This design uses a BiCMOS technology that provides a 47 GHz f/sub t/ SiGe HBTs and 250 nm CMOS. Results are based on circuit level SpectreS simulations in Cadence, with foundry provided transistor models.

A 12-bit 65 MS/s pipeline A/D converter in 0.18 μm SiGe BiCMOS

This work discusses the benefits of a SiGe BiCMOS implementation over a CMOS implementation for pipeline A/Ds. While various circuit blocks in a pipeline A/D can benefit from the higher transconductance (gm), higher unity gain frequency (fT) and lower noise of SiGe HBTs, this work focuses on the most critical block in a pipeline A/D, the operational transconductance amplifier (OTA). An OTA employing an all NMOS pre-amplifier followed by a cascoded SiGe HBT stage with actively cascoded PMOS loads is designed. A prototype 12-bit pipeline A/D achieves a measured SNDR of 62.6 dB and a SFDR of 73.4 dB at 65 MS/s with a power dissipation of 325 mW and operates from dual 1.8 V and 3.3 V supplies.

A 12-bit, 50 MS/s SiGe BiCMOS sample-and-hold residue amplifier

A 3.3 V, fully differential, switched-capacitor, gain-of-2, SiGe BiCMOS, sample-and-hold amplifier (SHA) for use as a residue amplifier in a 1.5-bit per stage pipeline A/D converter is presented. The SHA is realized by using an operational transconductance amplifier (OTA) in a closed loop negative feedback system. The SiGe BiCMOS OTA has a simulated DC gain of 88 dB with a unity gain frequency (f/sub T/) of 0.5 GHz at a phase margin of 65 degrees. The OTA has a differential output swing of 3 V and its differential input referred noise power spectral density (PSD) is 3.62 nV//spl radic/Hz. The SHA output settles to 0.01% accuracy in 9 ns, which allows realization of a 12-bit, 50 MS/s pipeline A/D converter (with an SNR /spl ap/ 72.6 dB) even without digital self-calibration. High performance is obtained by optimal use of SiGe HBTs as cascodes. In earlier work, a pipeline A/D converter fabricated in the same technology achieved 12-bit performance at 34 MS/s. The IBM 6HP technology provides 47 GHz SiGe HBTs and 250 nm CMOS.