Kenneth W. Martin

High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling /spl Delta//spl Sigma/ ADCs for broad-band applications

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

Small side-lobe filter design for multitone data-communication applications

An approach for realizing filter banks having improved side-lobe performance compared to approaches such as those based on inverse Fourier transforms (IFTs), especially for greater frequency differences from the passband frequencies, is presented. The approach is based on using a weighted-sum of near-adjacent IFT filters to realize the individual channel-bank filters, but with constraints added that results in significantly improved stopband performance while still achieving small reconstruction errors. The proposed channel banks are suitable for realizing multitone digital data communication systems, such as Asymmetric Digital Subscriber Line (ADSL) systems, where stopband performance is critical. Under the conditions of maximal decimation, the reconstruction is not perfect, but aliasing errors are small enough to be negligible in practical communication systems. For some cases, the filter coefficients can be determined exactly without using optimization. Given the frequency-weighting coefficients reported herein, near-optimal multirate filter banks may be designed exactly without optimization for all even n.

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.

A Q-enhanced active-RLC bandpass filter

The passive elements R, L, and C are combined with an amplifier to realize a high-Q bandpass filter. Positive feedback is used to enhance the finite Q of the lossy integrated inductors, and design equations are given that take into account the finite gain and finite bandwidth of the amplifier. It is shown that a quality factor of 20 at 1 GHz is possible with 10-GHz transistors. Preliminary noise analysis indicates promising results.<<ETX>>

BiCMOS circuits for analog Viterbi decoders

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8 /spl mu/m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5 V power supply.

Adaptive filters suitable for real-time spectral analysis

New cascade structures for adaptive filters are presented. They are especially suitable for real-time applications. Since the new structures are intended to be realized using single-chip DSP ICs or single-chip custom VLSI circuits, the requirements for memory and divisions are minimized. The new structures are based on state-variable biquads that in addition to having good SNRs and low sensitivities (for fixed-point implementations) can also have their resonant frequencies and Q-factors independently tuned. The special cases of using the adaptive filters for tracking sinusoids corrupted by noise and for formant based speech compression are described in detail.

A High-Speed Fully-Integrated POF Receiver With Large-Area Photo Detectors in 65 nm CMOS

This paper describes the design of a multi-gigabit fiber-optic receiver with integrated large-area photo detectors for plastic optical fiber applications. An integrated 250 μm diameter non-SML NW/P-sub photo detector is adopted to allow efficient light coupling. The theory of applying a fully-differential pre-amplifier with a single-ended photo current is also examined and a super-Gm transimpedance amplifier has been proposed to drive a C PD of 14 pF to multi-gigahertz frequency. Both differential and common-mode operations of the proposed super-Gm transimpedance amplifier have been analyzed and a differential noise analysis is performed. A digitally-controlled linear equalizer is proposed to produce a slow-rising-slope frequency response to compensate for the photo detector up to 3 GHz. The proposed POF receiver consists of an illuminated signal photo detector, a shielded dummy photo detector, a super-Gm transimpedance amplifier, a variable-gain amplifier, a linear equalizer, a post amplifier, and an output driver. A test chip is fabricated in TSMCs 65 nm low-power CMOS process, and it consumes 50 mW of DC power (excluding the output driver) from a single 1.2 V supply. A bit-error rate of less than 10-12 has been measured at a data rate of 3.125 Gbps with a 670 nm VCSEL-based electro-optical transmitter.

A 4-Gbps POF Receiver Using Linear Equalizer With Multi-Shunt-Shunt Feedbacks in 65-nm CMOS

This brief describes the design of a monolithic plastic optical fiber (POF) receiver with a pair of 250-by-250 μm N-well/P-sub photodetectors (PDs). A two-stage continuous-time linear equalizer that utilizes multiple active shunt-shunt feedback networks has been proposed to compensate for the slow-rolling-off high-frequency losses of the PDs. A test chip has been implemented in a standard 65-nm CMOS process, and it consists of a transimpedance amplifier, a variable-gain amplifier, a linear equalizer, a limiting amplifier, and an output buffer. The receiver consumes an active chip area of 0.24 mm2 and a dc power of 46 mW (excluding auxiliary test circuits and the output buffer) from a 1-V power supply. The prototype POF receiver demonstrates a non-return-to-zero data rate of 4 Gbit/s with a bit error rate less than 10-12, at a peak-to-peak optical input power of - 3.2 dBm p-p (average input power is kept at -3 dBm).

Analog front-end for a 3 Gb/s POF receiver

This paper describes a receiver front-end that is designed to realize multi-gigabit data communication via large-core plastic optical fiber (POF) in deep submicron CMOS technology. A 3D system-level integration scheme and transistor level circuits have been proposed for such a low-cost, high-speed POF receiver. With 44 mW (excluding output driver) DC power dissipated from a 1.2 V supply and an estimated 13 pF photo capacitance (CPD) from a discrete, large-area (400 um) photo detector (PD), a data rate of 3 Gbps, with a sensitivity of −11 dBm (BER = 10−12), has been simulated in STMicroelectronics (STM) 65 nm low-power CMOS technology.

Mismatch compensation techniques using random data for time-interleaved A/D converters

Offset, gain, and sample-time mismatches among different channels of a time-interleaved analog-to-digital converter (ADC) are causes of significant degradation of performance. Compensation techniques for offset mismatch, gain mismatch, and sample-time error in time-interleaved ADCs are proposed. The compensation methods use random digital data and do not use a calibration signal. The offset and gain mismatches are corrected in digital domain, while the timing error correction is performed by adjusting the delay of the clock path of each channel, using a digitally-controlled delay element. The simulation results verify that the proposed compensation techniques estimate and correct offset mismatch, gain mismatch and timing error with a high degree of accuracy. These low complexity techniques are especially suitable for time-interleaved ADCs used in digital data communication systems