Keping Chen

Bit-serial realizations of a class of nonlinear filters based on positive Boolean functions

It is shown that the function of a stack filter can be realized in k-step recursive use of one binary processing circuit. The time-area complexity of the proposed filter is O(k) as compared with O(2/sup k/) for stack filters. The proposed digital realizations are simple and modular in structure, and suitable for VLSI implementation. Analog/digital (A/D) hybrid realizations have the advantage that there is no need for an A/D converter array when the original signals come from an integrated sensor array. An experimental digital rank-order filter with a window size of three and arbitrary number of input bits is designed and implemented in a 3- mu m double-metal polysilicon gate CMOS process. The chip has been fabricated and measurement results are correct with a clock frequency of up to 110 MHz. >

PASIC: A processor-A/D converter-sensor integrated circuit

The design of an integrated smart sensor called PASIC is described. The basic idea is to integrate a 2-D image-sensor array with a linear A/D (analog-to-digital) converter array and a linear processor array in a single chip. The current version of PASIC contains 128 parallel processors with a 128*128-b memory, 128 8-b A/D converters, and a 128*128 photo sensor array. Two 128*8 bidirectional shift registers are used for communication between processor elements and I/O (input/output). A memory-bus organized architecture is used, having been proven as an efficient VLSI architecture for a SIMD (single instruction, multiple data) bit-serial processor array.<<ETX>>

Single-chip image sensors with a digital processor array

The architectures, implementation and applications of two smart sensors, LAPP and PASIC, are described. The basic idea of these two designs is to integrate an image sensor array with a digital processor array in a single chip. The integrated camera-and-processor eliminates the bottleneck of sequential image read-out that characterizes conventional systems. They provide fast, compact and economic solutions for tasks such as industrial inspection, optical character recognition and robot vision.

A parallel A/D converter array structure with common reference processing unit

A successive-approximation A/D converter array with a parallel architecture is proposed. The circuit is realized using a switched-capacitor (SC) technique. The architecture of the array is based on a common-reference processing unit and multichannel parallel-input, signal processing units. The latter, which are the main part of the array, are insensitive to the capacitor ratio mismatch and the gain of the amplifiers. The linearity of the array is insensitive to parasitic capacitors and offset of the amplifiers. The conversion time is linearly proportional to the number of bits required. Due to the small number of components needed and the simplicity of the circuit realization, the proposed A/D solution is suitable for VLSI implementation. A typical application would be in a small sensor system, where a sensor array, parallel A/D converters, and parallel digital processors are integrated in a single chip. >

Linear, polynomial and exponential ramp generators with automatic slope adjustment

A novel method for an automatic slope adjustment of ramp generators is presented. The method has been verified by functional chip implementations of both a linear and an exponential ramp generator in a 2 /spl mu/m standard CMOS process. Applying start and stop voltages to the ramp generator, the ramp will automatically adjust itself, and the time for a complete ramp is set by the pulse length of a clock signal. Such a ramp generator needs no trimming, and is insensitive to component values and ratios. Ramp forms that are functions of a linear ramp are obtainable, such as linear, exponential, and polynomial increasing ramp shapes. >

A CMOS implementation of a video-rate successive approximation A/D converter

Previous approaches to video-rate CMOS A/D (analog-to-digital) converters are based on fully-parallel, subrange, or pipeline architectures. The authors describe a 5-MHz 8-bit experimental design of a successive-approximation A/D converter using 3- mu m CMOS technology. Since neither capacitors nor a resistor string are needed in the current-switching technique, a conventional digital technology can be used. The use of the CMOS current-switch technique makes bipolar input signals possible. A circuit realization of a high-speed successive approximation register is also presented, using a single phase clock. The proposed technique is compatible with digital VLSI technology.<<ETX>>

Realizations of a class of nonlinear filters using a bit-serial approach

A bit-serial architecture for a class of nonlinear filters is proposed. The class of filters contains all of the functions defined by stack filters, where rank-order and median filters and special cases. The digital realizations are simple and modular in structure, suitable for VLSI/LSI implementation. An experiment on an LSI implementation of rank-order function is described.<<ETX>>

Fast algorithm for the calculation of image moments in a linear processor array

To compute moments of a two-dimensional image, a large number of multiplications and additions are required. High speed can be achieved with a parallel algorithm that can be implemented efficiently on a parallel processor array. An efficient algorithm for calculating the low-order moments is proposed for a linear processor array. Multiplications, which are the time-consuming operations, are completely avoided. The proposed algorithm exhibits rich parallelism and is well suited to be implemented in a SIMD linear processor array.<<ETX>>

High speed pipelined CMOS encoder for flash A/D converters

Different CMOS encoders for flash A/D (analog-to-digital) converters are compared from the speed and noise points of view. The proposed pipelined CMOS encoder gives a load capacitance to each comparator of no more than a unit inverter. The error probability of the encoder in the most significant bit is much less than that in the least significant bit. A true single-phase clock was used to achieve high speed and simple structure. A 6-bit flash A/D converter using very simple, nonlatched comparators associated with this encoder was fabricated in a 3- mu m CMOS process and tested. The highest sampling rate measured was 200 megasamples/s at a power supply of +or-3.5 V.<<ETX>>

Z-domain synthesis of switched-capacitor LDI ladder filters

A Z-domain two-port flowgraph synthesis method for switched-capacitor (SC) ladder filters is described. This approach for the design of lossless-dielectric-integrator (LDI) ladder filters is, compared to other methods, general and flexible. The proposed method can lead to a design of a locally nonreciprocal and globally reciprocal network. Both conventional switched-capacitor ladder filters and new switched-capacitor realizations can be designed using this approach. It is concluded that the advantages of these novel SC filter realizations can be exploited when the filters are implemented using integrated MOS technology.<<ETX>>