Keun-Soo Song

A single-loop DLL using an OR-AND duty-cycle correction technique

In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type [5] with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise-management technique of VPP control and by using a pseudo-rank architecture to suppress VDD noise due to low VPP pumping efficiency.

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme and Duty-Training Circuit (DTC) is presented. A Low Voltage-Swing Terminated Logic (LVSTL) driver using 4-to-1 multiplexer is implemented to the transmitter. A DTC to adjust the CK duty is implemented to the receiver. In addition, a ZQ calibration scheme for Multi-VOH level is also presented. Designed schemes are compatible with the LPDDR4 standard. Power efficiency for the I/O interface is about 2.3mW/Gb/s/pin with 1.1V supply in 2y-nm DRAM process, which is 31% lower than that of LPDDR3.

A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

A floating tap termination scheme with inverted DBI AC and floating tap forcing technique for high-speed low-power signaling

This paper presents a novel floating tap termination (FTT) scheme with inverted data bus inversion (iDBI_AC) and floating tap forcing (FTF) to remove the DC current path, leading to reduction of static current. The iDBI_AC and FTF are proposed to resolve common-mode stabilization issues for the floating tap termination scheme during transmitting unbalanced data patterns. Power efficiency with the proposed scheme using 0.6V I/O supply and a 0.13-um technology is measured as 0.127mW/Gbps/pin, which is 61% lower than that of a low tap termination (LTT) scheme used in LPDDR4X. In addition to the power benefit, measurement results present that the proposed scheme leads to achieve 7Gbps data-rate without penalty of signal integrity issues and the iDBI_AC minimizes inter-symbol interference (ISI).

A 2.3-mW 0.01-mm

In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm2 while consuming 2.27 mW from a 1.0-V supply.