Keun Soo Yim

A flash compression layer for SmartMedia card systems

Flash memory based SmartMedia card is becoming increasingly popular as data storage for mobile consumer electronics. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in flash memory is challenging because it only supports page-based I/Os. For example, when the size of compressed data is smaller than the page size, internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we developed a flash compression layer (FCL) for the SmartMedia card systems. FCL stores several small compressed pages into one physical page by using a write buffer. Based on prototype implementation and simulation studies, we show that the proposed system offers the storage of flash memory more than 140% of its original size and expands the write bandwidth significantly.

A fast start-up technique for flash memory based computing systems

Flash memory based embedded computing systems are becoming increasingly prevalent. These systems typically have to provide an instant start-up time. However, we observe that mounting a file system for flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time. Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the in-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast crash recovery techniques when the snapshot is invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system.

CATA: a garbage collection scheme for flash memory file systems

The problem of flash memory is that it cannot be overwritten unless erased in advance. In order to avoid having to erase during every update, non-in-place-update schemes have been widely used. In case of non-in-place update mechanism, garbage collection is needed to reclaim the obsolete space. In this paper, we study a new garbage collection scheme to reduce its cost such as the number of erase operations and the number of data copies. The proposed scheme determines the victim blocks by exploiting usage information of data blocks such as age, utilization and erase count. In addition, the proposed scheme predicts the future I/O workload and controls the number of victims to avoid disturbing the normal I/O operations. Experimental results show that the proposed scheme can perform well especially when the degree of locality is high.

An energy-efficient routing and reporting scheme to exploit data similarities in wireless sensor networks

Wireless sensor networks are based on a large number of tiny sensor nodes, which collect various types of physical data. These sensors are typically energy-limited and low-power operation is an important design constraint. In this paper, we propose a novel routing and reporting scheme based on sample data similarities commonly observed in sensed data. Based on reliable transport protocols, the proposed scheme takes advantage of the spatial and temporal similarities of the sensed data, reducing both the number of sensor nodes that are asked to report data and the frequency of those reports. Experimental results show that the proposed scheme can significantly reduce the communication energy consumption of a wireless sensor network while incurring only a small degradation in sensing accuracy.

Operating System Support for Procedural Abstraction in Embedded Systems

Procedural abstraction reduces code size by replacing repeated code fragments with call instructions to a subroutine that executes the repeated fragment. However, in order to build a subroutine, extra instructions are necessary to support the procedural call mechanism. In this paper, we present an operating system level technique which improves the space efficiency of a procedural abstraction-based code compaction technique. The call-related extra instructions are not used in the proposed technique because operating system routines implicitly supports the procedure call and return. The proposed technique consists of three execution modes including one applicable to ROM-based systems. The experimental results show the proposed technique reduces the code size significantly while increasing the execution time slightly

A space-efficient on-chip compressed cache organization for high performance computing

In order to alleviate the ever-increasing processor-memory performance gap of high-end parallel computers, on-chip compressed caches have been developed that can reduce the cache miss count and off-chip memory traffic by storing and transferring cache lines in a compressed form. However, we observed that their performance gain is often limited due to their use of the coarse-grained compressed cache line management which incurs internally fragmented space. In this paper, we present the fine-grained compressed cache line management which addresses the fragmentation problem, while avoiding an increase in the metadata size such as tag field and VM page table. Based on the SimpleScalar simulator with the SPEC benchmark suite, we show that over an existing compressed cache system the proposed cache organization can reduce the memory traffic by 15%, as it delivers compressed cache lines in a fine-grained way, and the cache miss count by 23%, as it stores up to three compressed cache lines in a physical cache line.

An Energy-Efficient Reliable Transport for Wireless Sensor Networks

In a wireless sensor network, sensor devices are connected by unreliable radio channels. Thus, the reliable packet delivery is an important design challenge. The existing sensor-to-base reliable transport mechanism, however, depends on a centralized manager node, incurring large control overheads of synchronizing reporting frequencies. In this paper, we present a decentralized reliable transport (DRT) with two novel decentralized reliability control schemes. First, we propose an independent reporting scheme where each sensor node stochastically makes reporting decisions. Second, we describe a cooperative reporting scheme where every sensor node implicitly cooperates with its neighbors for the uniform reporting. In the reporting step, DRT uses a reliable MAC channel, which is specifically optimized for reducing the energy dissipation. Experimental results show that DRT satisfies the desired delivery rate reliably in a decentralized manner while it significantly reduces the energy consumption of the radio device and the communication time.

A software reproduction of virtual memory for deeply embedded systems

Both the hardware cost and power consumption of computer systems heavily depend on the size of main memory, namely DRAM. This becomes important especially in tiny embedded systems (e.g., micro sensors) since they are produced in a large-scale and have to operate as long as possible, e.g., ten years. Although several methods have been developed to reduce the program code and data size, most of them need extra hardware devices, making them unsuitable for the tiny systems. For example, virtual memory system needs both MMU and TLB devices to execute large-size program on a small memory. This paper presents a software reproduction of the virtual memory system especially focusing on paging mechanism. In order to logically expand the physical memory space, the proposed method compacts, compresses, and swaps in/out heap memory blocks, which typically form over half of the whole memory size. A prototype implementation verifies that the proposed method can expand memory capacity by over twice. As a result, large size programs run in parallel with a reasonable overhead, comparable to that of hardware-based VM systems.

NIC-NET: a host-independent network solution for high-end network servers

This paper discusses a host-independent network system where a network interface card is utilized in an efficient way. By eliminating protocol stack processing overheads from host system, the proposed system improves the communication speed by 11-36% under heavy network and CPU loads.