Jae Cheol Son

28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

This paper presents a heterogeneous configuration of two different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of quad-core CPUs are implemented in one mobile application processor. The first type quad-core CPU is designed to give the highest performance at the cost of reasonable power consumption. The second type quad-core CPU is optimized with emphasis on energy efficiency than high performance. This paper addresses the design features for high-performance quad-core CPU and the design optimization issue for low-power quad-core CPU. The best performance shows 1.8X of performance at the lowest power. The lowest power is reduced to 1/5 of power at the highest performance. Our heterogeneous configuration of separate implementations can be a more efficient solution for different power and performance requirements of various mobile applications.

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

The proliferation of high-performance mobile devices is growing exponentially around the world. The essential driving force behind these ubiquitous devices is the high-performance CPU. To satisfy ever growing consumer demand for higher performance, a high-speed and multicore CPU configuration is mandatory, while energy efficiency is equally important for longer battery life. Furthermore, in order to support the wide range of performance (compute-intensive tasks, as well as less intensive tasks) required by todays mobile devices, a heterogeneous dual-CPU configuration comprising a high-performance CPU and an energy-efficient CPU can be one of the most energy efficient solutions for accomplishing both high-intensity and low-intensity tasks.

A 32nm high-k metal gate application processor with GHz multi-core CPU

Samsungs next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs are needed to meet this demand. Furthermore, mobile GPU performance is becoming increasingly important as mobile game graphics requirements are pushing the limits of GPU capabilities. For an enhanced mobile game user experience, a multi-core GPU is required. CPU/GPU power efficiency for longer battery life has been a major interest to consumers for many years. In order to support higher performance and power efficiency, two 64b quad-core CPUs with different microarchitectures and a hexa-core GPU are implemented using Samsungs 20nm gate-last high-k/metal-gate (HKMG) process.

A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices

This article introduces a 32 nm application processor designed for the latest high-performance smart handheld devices and discusses its design targets and options. To meet unprecedented levels of performance and data throughput demands, this processor employs a 200 MHz-1.6 GHz quad-core CPU, a quad-core GPU, a 2-port interleaving DRAM controller, dedicated video/audio/image processors, a camera/ display controller, and a hierarchical bus. This processor does it in a given power budget and battery life, and also in a given thermal budget by combining 32 nm high-k metal gate process technology with system-level power management techniques and dynamic thermal management techniques.

Comparative study of test generation methods for simulation accelerators

Hardware-accelerated simulation platforms are quickly becoming a major vehicle for the functional verification of modern systems and processors. Accelerator platforms provide functional verification with valuable simulation cycles. Yet, the high cost and limited bandwidth of accelerator platforms dictate a requirement for continuous utilization improvement. In this work, we perform a comparative analysis of two approaches of test generation for accelerator platforms. An exerciser tool is used as experimental vehicle for the study. An off-platform test generation methodology is implemented and is compared to on-platform test generation typically used in exercisers. We present experimental results from simulation of latest IBM POWER8 processor on Awan accelerator platform, as well as from simulation of an eight-core ARMv8-based design on Veloce emulation platform. Our results indicate that the utilization of accelerator platforms can be improved by up to ×7 ratio when using off-platform test generation. In addition, increase of up to 24% is observed in test coverage. Off-platform mode features significantly bigger image size, but maintains tolerable build and load times.

Scan-controlled pulse flip-flops for mobile application processors

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

Low-power dual-supply clock networks with clock gating and frequency doubling

Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%.

Fully digital clock frequency doubler

This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650 MHz to 1.25 GHz.

Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms

Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents an off-platform test generation method and it compares and contrasts it against the on-platform alternative for two state-of-the-art multicore processor designs.