Ki Seog Kim

Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability

We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.

Improvement of Data Retention in NAND Flash Memory for beyond 3x nm using HTO Liner and IPD Thickness Optimization

As cell size shrinks in NAND Flash memory, assuring adequate reliability characteristics is getting difficult due to the sensitivity of Flash cell against small process changes. Especially, it is still unclear how the combination of mechanical stresses encapsulating the cell structure affects the reliability characteristics. In this paper, we present our results on how to improve reliability with optimizing mechanical stress in active and interpoly dielectrics (IPD) thickness, and confirmed the results through various simulations and test methods on 41nm NAND technology. Hereafter, we need to fully confirm the ISO and IPD beyond 3x nm technology node.