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Dive into the research topics where Kevin Lyne is active.

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Featured researches published by Kevin Lyne.


custom integrated circuits conference | 2005

Cellular handset integration - SIP vs. SOC and best design practices for SIP

Kevin Lyne

There has recently been much discussion regarding the pros and cons of Silicon on Chip (SOC) versus System in Package (SW). SOC is firstly driven by cost reduction and secondly by miniaturization. This involves cost reduction at component level as well at system (handset) level. Cost reduction comes from a reduction of total component count, both ICs and passives, as well as reduction in mother board area. Further cost avoidance comes from a bill of materials with few components, giving the benefits of lower surface mounting costs, and lower inventory overhead. Similarly, SW can offer some of these benefits. However, in most cases, the primary motivation for SW is miniaturization, rather than cost reduction. An aggressive goal for a SIP product would be to achieve the same cost for the SIP as the sum of the elements integrated in to the SW. Even if this aggressive cost goal is not achieved, the benefits from the miniaturization are frequently sufficient to justify the development of a SIP product. In reality, there is no conflict between the SOC and SIP technologies. Many times both techniques are employed synergistically. This paper continues this SOC vs SIP discussion, focusing on SIP, and demonstrating the synergism between the two


Archive | 2001

Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified

Kevin Lyne


Archive | 2007

Package on package design a combination of laminate and tape substrate, with back-to-back die combination

Kevin Lyne


Archive | 1999

Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability

Kevin Lyne


Archive | 2007

Multiple die integrated circuit package

Kevin Lyne


Archive | 2008

Bga package with traces for plating pads under the chip

Kenneth Robert Rhyner; Kevin Lyne; David G. Wontor; Peter R. Harper


Archive | 2012

3D Semiconductor Interposer for Heterogeneous Integration of Standard Memory and Split-Architecture Processor

Kevin Lyne; Kurt P. Wachtler


Archive | 2007

Simplified Substrates for Semiconductor Devices in Package-on-Package Products

Peter R. Harper; James L. Turner; Kevin Lyne; Kurt P. Wachtler


Archive | 2010

SEMICONDUCTOR WAFER CHIP SCALE PACKAGE TEST FLOW AND DICING PROCESS

Kevin Lyne; Stanley Craig Beddingfield; Elida I. De Obaldia; Raymundo Monasterio Camenforte; David Charles Stepniak


Archive | 2006

Device and method for including passive components in a chip scale package

Kevin Lyne

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