Kevin W. Gorman

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.

Generating At-Speed array fail maps with low-speed ATE

A circuit has been developed to accurately generate embedded memory fail maps utilizing At-Speed test clocks generated from low-speed automated test equipment (ATE). The circuit provides a simple interface to communicate between the BIST and ATE for fail data collection. The BIST engine utilizes on-chip clock frequency multiplication to exercise the memory At-Speed. The described implementation reduces test time devoted to creating detailed fail maps in manufacturing by providing the ability to run the part At-Speed, and providing a means to collect fail map data in one test pass on a logic tester.

Embedded DRAM in 45-nm Technology and Beyond

As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.

Advancements in at-speed array BIST: multiple improvements

This paper discusses the unique challenges in constructing an architecture and methodology for testing a 1 GHz 65 nm Embedded DRAM in an ASIC environment. The concepts of multiplication of both test commands and test clock frequency are discussed in detail. The novel technique of command multiplication is thoroughly explored. The inherent benefits of this design point is examined as it relates to test circuit design, BIST sharing, and chip level wiring in comparison to traditional scan or parallel based array BIST architectures. Attention is also paid to various methods used for supporting at-speed/high-speed test clock generation from a low speed tester and the important influence this has on test cost and test quality.

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.

Low Cost Test of High Bandwidth Embedded Memories

This work presents architectures and methods necessary for providing efficient and thorough test of high bandwidth embedded memories using low speed ATE. Details are also provided on the techniques used to minimize test related silicon area and test time requirements. This combination of flexible at-speed test with minimal circuitry and ATE requirements, and reduced time under test, leads to lower cost production of embedded memories

Optimizing delay tests at the memory boundary

Delay faults on the inputs and outputs of memories embedded in an integrated circuit are difficult to cover efficiently in manufacturing test. A complicated approach, separate from standard digital logic tests or memory built-in self-test, is needed to target these faults and further improve manufacturing quality. This paper discusses some of the challenges of implementing this approach and the design-for-test changes we made to the memories and to the surrounding logic to address these challenges. Our optimized method for testing the boundaries of repaired memories is presented. Our implementation has been validated and is included in our standard manufacturing test suite. It improves tests for delay faults on the memory functional boundary by minimizing the capture of unknown data, simplifying the test sequences, and testing different memory types in parallel. Results from five 32nm industry parts show that our method enables entirely automatic generation of a compact set of high-coverage test patterns for any integrated circuit design.

Practical Application of RAM Sequential Test

With the growing number and speed of embedded memories, testing for delay defects in the logic surrounding RAMs is becoming increasingly important. This article introduces DFT techniques for testing the transition faults at the memory functional boundary.