Jeffrey H. Dreibelbis

Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256/spl times/16/spl times/128 to 2 K/spl times/16/spl times/256 (Word/spl times/Bit/spl times/Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations.

An ASIC library granular DRAM macro with built-in self test

System-on-a-chip architectures are generating increased interest as the level of integration is expanded by the arrival of 0.25 /spl mu/m processes. Many merged DRAM and logic applications use custom logic circuits that either surround or are embedded in a DRAM core. A more classic ASIC library approach where a DRAM macro family is used as a logic building block with the software tools associated with ASIC logic macros: i.e., timing analysis, place-and-route, logic simulation, and test generation. The macro operation is generic, yet versatile, allowing gate-array or standard-cell interface personalization. The design has a wide databit interface of 128 or 256 bits, separate databit-in and databit-out to ease bus contention, bit-write capability for multiplexing to narrower databit widths or partial databit-writes, and granular-density options from 0.5 Mb-8 Mb. Built-in self test (BIST) with two-dimensional redundancy calculation and allocation, along with in-situ burn-in capability, is also included. The DRAM macro design is architectured for reuse on future DRAM-generation sub-arrays and is adaptable to any number of address or databit-pin configurations. Its methodology and functionality have been verified in a 0.45 /spl mu/m trench DRAM technology.

Embedded DRAM built in self test and methodology for test insertion

As ASIC technologies expand into new markets, the need for dense embedded memory grows. To accommodate this increased demand, embedded DRAM (eDRAM) macros have been offered in state-of-the-art ASIC library portfolios. This integration of eDRAM into ASIC designs has intensified the focus on how best to test a high density macro as complex as DRAM in a logic test environment. The traditional use of Direct Memory Access (DMA) is costly in silicon area, wiring complexity, and test time. A more attractive solution to this test problem is the use of a Built-In Self Test (BIST) system that is adapted to provide all the necessary elements required for high fault coverage on DRAM, including the calculation of a two-dimensional redundancy solution. pattern programming flexibility, at speed testing, and test mode application for margin testing. This paper presents an overview of the BIST implemented as part of IBMs third generation eDRAM for the 0.13 /spl mu/m ASIC design system. A special emphasis on test pattern integration into the test flow is discussed which describes a developed methodology for taking test patterns from the conceptual stage, through validation, to inclusion in the production test flow.

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic® 0.11-µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.

Test and repair of large embedded DRAMs. 2

Embedded DRAM offers major advantages in terms of system integration on-chip. However, the fabrication process requires special attention for profitable manufacturing, particularly in the area of test and repair. We present the benefits which embedded DRAM offers, and then move to test issues. We provide an analysis of the technical and financial impact of different test approaches, and discuss which considerations are important in choosing a test strategy.

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.

Multipurpose DRAM architecture for optimal power, performance, and product flexibility

An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3 .34 or 5.04 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1 Mb x 16 operation with 2Mb x 8, 4Mb x 4, and 4Mb x 4 with any 4Mb independently selectable (4Mb x 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.

BIST-based bitfail mapping of an embedded DRAM

Trends in system-on-a-chip (SOC) semiconductor design and fabrication have complicated many well-established test processes. Circuits such as DRAM memories, which have been tested for decades on dedicated memory testers, using sophisticated test programs and patterns, may no longer be testable with such established methodologies. Testing and diagnosing embedded DRAM (eDRAM) memories is no less important in an SOC model than it was in a discrete DRAM model. In this paper we describe and evaluate a technique for doing bitfail-map-based diagnostics of an eDRAM, and demonstrate success in physical failure analysis (PFA).