Darren L. Anand

A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write

A 0.12 /spl mu/m growable eDRAM macro has GND sense, bit-line twisting, direct reference cell write, a flexible multi-banking protocol, and column redundancy to support multi-banking. The protocol supports simultaneous activate, read/write and pre-charge to three different banks. Hardware measurements verify 300 MHz operation, 6.6 ns tacc, and 10 ns trc.

Embedded DRAM built in self test and methodology for test insertion

As ASIC technologies expand into new markets, the need for dense embedded memory grows. To accommodate this increased demand, embedded DRAM (eDRAM) macros have been offered in state-of-the-art ASIC library portfolios. This integration of eDRAM into ASIC designs has intensified the focus on how best to test a high density macro as complex as DRAM in a logic test environment. The traditional use of Direct Memory Access (DMA) is costly in silicon area, wiring complexity, and test time. A more attractive solution to this test problem is the use of a Built-In Self Test (BIST) system that is adapted to provide all the necessary elements required for high fault coverage on DRAM, including the calculation of a two-dimensional redundancy solution. pattern programming flexibility, at speed testing, and test mode application for margin testing. This paper presents an overview of the BIST implemented as part of IBMs third generation eDRAM for the 0.13 /spl mu/m ASIC design system. A special emphasis on test pattern integration into the test flow is discussed which describes a developed methodology for taking test patterns from the conceptual stage, through validation, to inclusion in the production test flow.

An on-chip self-repair calculation and fusing methodology

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic® 0.11-µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.

Shared fuse macro for multiple embedded memory devices with redundancy

Customers designing increasingly complex integrated circuits are turning to ASIC vendors to help bring their products to market faster than their competitors. ASIC designs with large amounts of embedded memory must use fuse-enabled redundancy techniques to maintain price competitive yield. IBM has developed a data compression and shared fuse technique to accommodate large numbers of redundant elements in an ASIC. This technique minimizes or eliminates problems associated with a large number of fuses distributed within many embedded memories on an ASIC.

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns

A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for VDD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for VDD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock.

Generating At-Speed array fail maps with low-speed ATE

A circuit has been developed to accurately generate embedded memory fail maps utilizing At-Speed test clocks generated from low-speed automated test equipment (ATE). The circuit provides a simple interface to communicate between the BIST and ATE for fail data collection. The BIST engine utilizes on-chip clock frequency multiplication to exercise the memory At-Speed. The described implementation reduces test time devoted to creating detailed fail maps in manufacturing by providing the ability to run the part At-Speed, and providing a means to collect fail map data in one test pass on a logic tester.

Embedded DRAM in 45-nm Technology and Beyond

As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.