Khaled Ben Khalifa

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.

Multi-width fixed-point coding based on reprogrammable hardware implementation of a multi-layer perceptron neural network for alertness classification

This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL code within a multi-width encoding of an MLP. The proposed methodology should determine the optimal encoding of various blocks of our Artificial Neural Networks (ANN) to optimize accuracy and minimize the application area. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized MLP implementation has been tried on Virtex devices.

A Scalable Flexible SOM NoC-Based Hardware Architecture

In this paper , a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware \(5\times 5\) SOM was validated through the FPGA implementation and its performances at a working frequency of 200 MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.

A scalable and adaptable hardware NoC-based self organizing map

Abstract Due to their ability to reduce the size of high-dimensional input data, self-organizing maps (SOMs) can be employed as data quantizers. The widely used software implementations of SOM enjoy flexibility and adaptability, usually to the detriment of performances, which limits their use in real time applications. On the contrary, the hardware counterparts of SOMs exploit the inherent parallelism of hardware to boost the overall performances, but generally lack adaptability without considerable design efforts. To benefit from both, the flexibility of software and performances of hardware SOM implementations, unconventional design approaches of SOMs should be used. In this work, a scalable and adaptable hardware implementation of a SOM network is presented. The proposed architecture allows to dynamically extend the SOM operation from a smaller to a larger map only by (re-)configuring the parameters of each neuron. The gained scalability is obtained by decoupling the computation layer composed of neurons, from the communication one, used to provide data exchange mechanisms between neurons. The proposed SOM architecture is also validated through simulation on variable-sized SOM networks applied to image compression.

Implementation of a novel LVQ neural network architecture on FPGA

The current study presents the hard implementation methodology of a Learning Vector Quantization (LVQ) neural network on a Field Programmable Gate Array (FPGA) circuit specially suited for fast output applications. The implementation methodology is based on a mixed parallel sequential approach with the use of the L2 norm (Euclidian distance) to measure the distance between the reference vector and the prototype vector. The adopted architecture has been implemented on a device XCV1000 (FPGA Xilinx) and the given results have shown good performances in time, surface and consumption.

LVQ neural network optimized implementation on FPGA devices with multiple-wordlength operations for real-time systems

The development of hardware platforms for artificial neural networks (ANN) has been hindered by the high consumption of power and hardware resources. In this paper, we present a methodology for ANN-optimized implementation, of a learning vector quantization (LVQ) type on a field-programmable gate array (FPGA) device. The aim was to provide an intelligent embedded system for real-time vigilance state classification of a subject from an analysis of the electroencephalogram signal. The present approach consists in applying the extension of the algorithm architecture adequacy (AAA) methodology with the arithmetic accuracy constraint, allowing the LVQ-optimized implementation on the FPGA. This extension improves the optimization phase of the AAA methodology by taking into account the operations wordlength required by applying and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. This LVQ implementation will allow a considerable gain of circuit resources, power and maximum frequency while respecting the time and accuracy constraints. To validate our approach, the LVQ implementation has been tried for several network topologies on two Virtex devices. The accuracy–success rate relation has been studied and reported.

A hardware configurable self-organizing map for real-time color quantization

Real-time color quantization requires high performances and high configurability. Self-organizing maps (SOMs) are very suited as color quantizers. However, widely used software SOM quantizers are flexible with limited performances, whereas the hardware counterparts lack in flexibility. In this work, we propose a flexible and adaptable real-time hardware implementation of a SOM map applied to color quantization. The proposed architecture allows to find iteratively, for each processed image, the adequate SOM structure providing optimal quality and performances. It is validated on a 16×16 map using 128×128 RGB images. The proposed reconfiguration allows to improve dynamically the PSNR of processed images by changing the structure of the SOM and its time is estimated to 38 clock cycles.

Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems: LVQ Implementation

The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. The AAA-MWOG methodology will allow a considerable gain of circuit resources. This contribution is demonstrated by implementing the Learning Vector Quantization (LVQ) neural-networks model on the FPGA. The LVQ optimization is used to quantify vigilance states starting from processing the electroencephalographic signal. The precision-gain relation has been studied and reported. Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems: LVQ Implementation