Slavisa Jovanovic

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.

CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs

In this article, we present CuNoC, a new paradigm for intercommunication between modules dynamically placed on a chip for FPGA-based reconfigurable devices. The CuNoC is based on scalable communication unit called CU which allows the simultaneous communication between several processing elements placed on the chip. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main NoC approaches already proposed.

A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems

In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total tasks register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at another time (and/or from another area of the FPGA in FPGA-based designs). The main advantages of the proposed method are that it provides an attractive way for context saving and restoring of a hardware task without freezing other tasks during pre-emption phases and a small area overhead. We show its feasibility by allowing us to design a simple computing example as well as the implementation of AES-128 encryption algorithm which are presented in and detailed on the Xilinx Virtex FPGA technology.

A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems

Networks on chip (NoCs) present viable interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are mostly destined to system-on-chip (SoCs) designs. For a FPGA-based reconfigurable system, the proposed NoCs are not suitable. In this paper, we present a new high-performance interconnection approach destined for FPGA-based reconfigurable system. Our proposed NoC is based on a scalable communication unit characterized by its particularly architecture, an arbitration policy based on the priority-to-the-right rule and high performances. We present the basic concept of this communication approach and we prove its feasibility on examples through the simulations. Implementation results are also detailed.

Design of power electronic digital controller based on FPGA/SOC using VHDL-AMS language

In this paper, authors detail a Top-down design methodology for Power Electronic digital controller based on Field Programmable Gate Aray or System-On-Chip. This design flow uses VHDL-AMS language. The application case of a shunt three phase power active filter is studied. An optimised architecture is designed and each step is detailed. Each block of the architecture is modeled in VHDL at several abstraction levels, from real data format to specific binary format. To achieve closed loop simulation, analog and power elements are modeled in VHDL-AMS. The whole closed loop system is successfully validated at various abstraction levels of the digital control, using ADVanceMS.

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.

Fully Electrical Modeling of Thermoelectric Generators with Contact Thermal Resistance Under Different Operating Conditions

The Seebeck effect is used in thermoelectric generators (TEGs) to supply electronic circuits by converting the waste thermal into electrical energy. This generated electrical power is directly proportional to the temperature difference between the TEG module’s hot and cold sides. Depending on the applications, TEGs can be used either under constant temperature gradient between heat reservoirs or constant heat flow conditions. Moreover, the generated electrical power of a TEG depends not only on these operating conditions, but also on the contact thermal resistance. The influence of the contact thermal resistance on the generated electrical power have already been extensively reported in the literature. However, as reported in Park et al. (Energy Convers Manag 86:233, 2014) and Montecucco and Knox (IEEE Trans Power Electron 30:828, 2015), while designing TEG-powered circuit and systems, a TEG module is mostly modeled with a Thévenin equivalent circuit whose resistance is constant and voltage proportional to the temperature gradient applied to the TEG’s terminals. This widely used simplified electrical TEG model is inaccurate and not suitable under constant heat flow conditions or when the contact thermal resistance is considered. Moreover, it does not provide realistic behaviour corresponding to the physical phenomena taking place in a TEG. Therefore, from the circuit designer’s point of view, faithful and fully electrical TEG models under different operating conditions are needed. Such models are mainly necessary to design and evaluate the power conditioning electronic stages and the maximum power point tracking algorithms of a TEG power supply. In this study, these fully electrical models with the contact thermal resistance taken into account are presented and the analytical expressions of the Thévenin equivalent circuit parameters are provided.

A thermoelectric energy harvester with a single switch unified control for autonomous applications

In the past decades, due to the increasing environmental concerns, many research works have targeted the use of energy harvesting technologies as an alternative to the fossil fuels. Free availability of heat makes harvesting energy from Thermoelectric Generators (TEGs) as one of the most viable sources of electricity. In a thermoelectric energy harvester, it is mandatory to perform Maximum Power Point Tracking (MPPT), aiming at maximizing the extracted energy irrespective of the temperature gradient conditions. The Open Circuit Voltage (OCV) MPPT method appears as the most widely used and suitable for TEGs. Moreover, the output voltage across the load must also be regulated. To perform MPPT and output voltage control simultaneously, conventional two-stage DC-DC converters are usually used. In this paper, we propose an unified control for a Single Switch DC-DC Converter (SSC), performing both, the MPPT and the output voltage control. Moreover, the reduction of the number of switches decreases the cost of the harvester as well as the size and the control complexity. The resulting harvester has been modeled and simulated; the results confirm the effectiveness and the robustness of the simultaneous MPPT and output voltage regulation.

MPPT and output voltage control of Photovoltaic systems using a Single-Switch DC-DC converter

This paper presents the simultaneous Maximum Power Point Tracking (MPPT) and output voltage regulation of a stand-alone Photovoltaic-battery-load power system, based on a Single-Switch DC-DC converter. In the literature, the well-known two-stage buck converter cascaded with a buck-boost one is mentioned as the most suitable non-isolated DC-DC converter for such a Photovoltaic (PV) system. Based on an unified approach to develop Single-Stage power converters, we propose to use an equivalent Single Switch Converter (SSC) for the studied PV system, thus increasing its reliability and decreasing the overall system cost, thanks to the reduced number of switches. In the same spirit, the MPPT algorithm has been chosen among the most used ones. The Perturb and Observe (P&O) algorithm appears as the best compromise, performing good tracking factor, simple implementation and satisfactory accuracy. The resulting PV system has been modeled and simulated; the results confirm the effectiveness and the robustness of the simultaneous MPPT and output voltage regulation.

Influence of contact thermal resistances on the Open Circuit Voltage MPPT method for Thermoelectric Generators

The thermoelectric effect has been appeared as an alternative source for electrical power generation. It has been used in Thermoelectric Generators (TEGs) to supply electronic circuits with the recovered thermal energy dissipated in an environment. A TEG is a device formed by the association of semiconductors that convert heat into electrical energy proportional to the temperature difference across it. In a simplified approach, a TEG can be modeled by a constant DC voltage source in series with its internal resistance; however, in a more accurate model, real internal contact thermal resistances must be considered. Maximum Power Point Tracking (MPPT) algorithms are used to extract the maximum power from a TEG during its operation. In the literature, the MPPT method relying on the Open-Circuit Voltage (OCV) is the most widely used and suitable for TEGs. The aim of the present paper is to evaluate the influence of contact thermal resistances on the OCV method used for the MPPT. Simulation results show that the OCV method tracks efficiently the maximum power point even when the contact thermal resistances in the TEG model, under constant temperature gradient conditions, are considered.