Khanh Tran
Maxim Integrated
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Publication
Featured researches published by Khanh Tran.
international electron devices meeting | 2013
Arkadii V. Samoilov; Khanh Tran; Nicole D. Kerness; Joy T. Jones; Peter McNally; Stanley Barnett; Tyler Parent; Joseph P. Ellul; Anu Srivastava; Kiyoko Ikeuchi; Tie Wang; Tiao Zhou
We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate the highest reported capacitor density of C=1 μF/mm2 (=1,000 fF/μm2) and the figure of merit (FOM) C*Vbd=11 C/m2 (Vbd is the breakdown voltage). Through-Si vias can be used to combine passive and active die into a single stack. Addition of optical layers to the Bipolar CMOS DMOS (BCD) process allows light detection in the visible and infrared range. 3D package-level integration is illustrated by embedding of multiple active and passive components in one package.
Archive | 2012
Joseph P. Ellul; Khanh Tran; Edward Martin Godshalk; Albert Bergemont
Archive | 2009
Joseph P. Ellul; Khanh Tran; Albert Bergemont
Archive | 2001
Viktor Zekeriya; Khanh Tran
Archive | 2013
Khanh Tran; Arkadii V. Samoilov; Pirooz Parvarandeh; Amit S. Kelkar
Archive | 2012
Khanh Tran; Joseph P. Ellul; Edward Martin Godshalk; Kiyoko Ikeuchi; Anuranjan Srivastava
Archive | 2012
Khanh Tran; Joseph P. Ellul; Anuranjan Srivastava; Kiyoko Ikeuchi; Scott Wilson Barry
International Symposium on Microelectronics | 2016
Amit S. Kelkar; Vivek S. Sridharan; Khanh Tran; Kiyoko Ikeuchi; Anu Srivastava; Viren Khandekar; Ricky Agrawal
Archive | 2014
Vivek S. Sridharan; Srikanth Kulkarni; Khanh Tran
Archive | 2010
Joseph P. Ellul; Khanh Tran; Albert Bergemont
