Khiem Nguyen

A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling

Consumer formats such as DVD push the performance of audio D/A converters to higher and higher levels. D/A converters with high dynamic range and low cost are now in demand. Previous /spl Sigma//spl Delta/ D/A converters have used 1b digital modulators with switched-capacitor analog filters. The noise of switched-capacitor filters is limited by thermal KT/C noise, so achieving high-dynamic range requires an impractical amount of on-chip capacitance. The design shown differs in several ways from previous /spl Sigma//spl Delta/ D/A converters. A continuous-time output stage avoids the thermal noise added by reasonable-size switched-capacitor circuits. Continuous-time /spl Sigma//spl Delta/ circuits have several serious problems, including high sensitivity to clock jitter, difficulty in filtering the output waveform, and extreme sensitivity to intersymbol interference in the pulse output waveform. These problems are reduced.

A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

An audio /spl Sigma//spl Delta/ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.

A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique

Previously reported multi-bit oversampling DeltaSigma audio DACs use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture.

A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique

A low power audio oversampling SigmaDelta digital-to-analog converter (DAC) with a three-level (+1, 0,-1) dynamic-element-matching (DEM) technique and an inter-symbol interference-free (ISI) output stage is presented. Solutions for design challenges such as ISI, clock jitter sensitivity, and out-of-band noise are presented. The converter is fabricated in a 0.18 mum CMOS process, occupies 0.55 mm2, achieves 108 dB dynamic range, -98 dB THD + N while consumes a total of 1.1 mW per channel at 1.8 V supply.

A 106dB SNR hybrid oversampling ADC for digital audio

A /spl Delta//spl Sigma/ ADC with a CT 1/sup st/-stage is presented. A hybrid tuning circuit adjusts the RC time constant to compensate for process, supply, and sampling rate variations. The ISI of the feedback DAC is eliminated by an RTZ scheme applied to the error current of the CT integrator. The ADC achieves 106dB SNR, -97dB THD+N, occupies 0.82mm/sup 2/ in a 0.35/spl mu/m CMOS process and dissipates 18mW.

A 113 dB SNR oversampling sigma-delta DAC for CD/DVD application

A sigma-delta (/spl Sigma//spl Delta/) audio digital-to-analog converter (DAC) for CD and digital versatile disk (DVD) application is presented. The converter uses a 6-bit modulator and a segmented noise-shaped scrambling technique to achieve a 113 dB dynamic-range over a 20 kHz bandwidth. A continuous-time output stage is used to achieve a high signal-to-noise (SNR) in a small die area. This output stage employs a dual return-to-zero scheme to eliminate errors caused by inter-symbol interference (ISI). The converter is fabricated in a 0.6 /spl mu/m double-poly double-metal CMOS process. The chip occupies 3.1/spl times/3.2 squared mm and operates from a single 5 V supply.

A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low power consumption such that the system can be housed in a small low-cost plastic package. Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1–3]. This paper presents a continuous time (CT) area- optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/chan-nel. This performance is achieved by using a new 3-level rotational data shuffling scheme which achieves small area and low digital activity at low signal level, and by applying low-power low-noise analog techniques.

A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications

A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.

Subtractive dithering technique for delta-sigma modulator

This paper presents a novel subtractive dithering technique used in delta-sigma modulators which improves the spectral integrity of the modulators while minimizing the tradeoffs due to the use of dither. Dithering is commonly used in delta-sigma modulators to eliminate idle tones. The proposed technique adds dither at input of the quantizer and subtracts the dither in the analog domain at input of the modulator and in the digital domain at the output of modulator. The simulation results prove that when compared to the conventional dithering technique, this new subtractive dithering technique achieves the idle tone-free result but does not have the traditional drawbacks such as increased integrator output swing and in-band noise floor degradation.

Practical dynamic element matching techniques for 3-level unit elements

• Optimized power consumption for DAC at low input level • Very effective first order DEM for the sub segment(s) • Very effective for DEM idle tone remedy • Trade off the gain accuracy across signal amplitude range (there is NO distortion because there is no switching back and forth between smaller DACs and the large DAC, on the fly). • Suitable for applications that require high AC linearity and not DC accuracy