Abhishek Bandyopadhyay

Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades

This paper describes a new predictive algorithm that can be used for programming large arrays of analog computational memory elements within 0.2% of accuracy for 3.5 decades of currents. The average number of pulses required are 7-8 (20 mus each). This algorithm uses hot-electron injection for accurate programming and Fowler-Nordheim tunneling for global erase. This algorithm has been tested for programming 1024times16 and 96times16 floating-gate arrays in 0.25 mum and 0.5 mum n-well CMOS processes, respectively

A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

We present a 128/spl times/32 four-quadrant programmable current-mode analog vector-matrix multiplier (VMM). The proposed multiplier cell operates on a 3.3 V supply, consumes 531 nW/MHz and is linear over two decades of current range. Programmability and non-volatile weight storage is obtained by using floating-gate transistors. Experimental results for a full image discrete cosine transform (DCT) using the proposed architecture is presented. The IC prototype was fabricated in a 0.5 /spl mu/m CMOS process and occupies 0.83 mm/sup 2/ of area.

Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method

This paper describes a new predictive algorithm that can be used for programming large arrays of analog computational memory elements within 0.2% of accuracy for 3.5 decades of currents. The average number of pulses required are 7-8 (20 /spl mu/s each). This algorithm uses hot-electron injection for accurate programming and Fowler-Nordheim tunneling for global erase. This algorithm has been tested for programming 1024/spl times/16 and 96/spl times/16 floating-gate arrays in 0.25 /spl mu/m and 0.5 /spl mu/m N-well CMOS processes, respectively.

A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression

We present a programmable 80 /spl mu/W/frame (3.3 V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc). Floating-gate technology is used for on-chip kernel storage and also for performing low-power current-mode matrix multiplications. We demonstrate this IC as a front-end for JPEG compression and compare the performance of this imager to fully digital approaches.

A matrix transform imager allowing high-fill factor

We present a transform imager that performs computation at the pixel plane, but still holds to a fill factor greater than 40 percent. This imager is capable of programmable matrix operations on the image, where we can represent the image as either a full matrix or using block matrix operations. Each pixel is composed of a photodiode sensor element and a multiplier. We present experimental data and results from a signal pixel, the resulting computation, and effect of mismatch and offsets through this circuit. We present the results of computing a DCT/DST transform, as well as frequency response characterizations related to these results.

A fully programmable CMOS block matrix transform imager architecture

In this paper, we introduce our CMOS block matrix transform imager architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill-factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (0.23 mW).

A CMOS floating-gate matrix transform imager

A new transform imager technology and architecture is introduced in this paper. This approach allows for retina and higher-level bio-inspired computation in a programmable architecture that still possesses similar high-fill factor pixels of APS imagers. This imager is capable of programmable matrix operations on the image, where the image can be presented as either a full matrix or using block matrix operations. Each pixel is composed of a photodiode sensor element and a multiplier. The core imager performs computation at the pixel plane but still holds to a fill factor greater than 46 %. The resulting data-flow architecture directly allows computation of spatial transforms, motion computations, and stereo computations.

High fill-factor imagers for neuromorphic processing enabled by floating-gate circuits

In neuromorphic modeling of the retina, it would be very nice to have processing capabilities at the focal plane while retaining the density of typical active pixel sensor (APS) imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our transform imager technology and basic architecture that uses analog floating-gate devices to make it possible to have computational imagers with high pixel densities. This imager approach allows programmable focal-plane processing that can perform retinal and higher-level bioinspired computation. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting dataflow architecture can directly perform computation of spatial transforms, motion computations, and stereo computations. The core imager performs computations at the pixel plane, but still holds a fill factor greater than 40 percent—comparable to the high fill factors of APS imagers. Each pixel is composed of a photodiode sensor element and a multiplier. We present experimental results from several imager arrays built in 0.5m process (up to in an area of 4 millimeter squared).

Image processing system using a programmable transform imager

We propose an image processing system using an analog transform imager chip. The transform imager is a CMOS imager which is capable of block transforms using floating-gates. Because the transform imager is highly programmable, it can perform various block transforms such as the Walsh-Hadamard transform, discrete sine transform (DST), and discrete cosine transform (DCT). We investigate the reduction of computations and power by a baseline JPEG compression system as an application. The 48/spl times/40 transform imager provides 144 MOPS/s using an area of 1.03 mm/sup 2/ in 0.5 /spl mu/m CMOS technology, and it has a much higher fill factor, 46%, compared with other focal plane imagers. The measured transformed images and the reconstructed images are presented to demonstrate the operations.

A matrix transform imager and architecture

We introduce our transform imager technology and architecture. This approach allows for retina and higher-level bio-inspired computation in a programmable architecture that still possesses similar high-fill factor pixels to APS imagers. This imager is capable of programmable matrix operations on the image, where we can represent the image as either a full matrix or using block matrix operations. The resulting data-flow architecture directly allows computation of spatial transforms, motion computations, and stereo computations. The core imager performs computation at the pixel plane. but still holds to a fill factor greater than 40 percent. Each pixel is composed of a photodiode sensor element and a multiplier.