Karl Sweetland

A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling

Consumer formats such as DVD push the performance of audio D/A converters to higher and higher levels. D/A converters with high dynamic range and low cost are now in demand. Previous /spl Sigma//spl Delta/ D/A converters have used 1b digital modulators with switched-capacitor analog filters. The noise of switched-capacitor filters is limited by thermal KT/C noise, so achieving high-dynamic range requires an impractical amount of on-chip capacitance. The design shown differs in several ways from previous /spl Sigma//spl Delta/ D/A converters. A continuous-time output stage avoids the thermal noise added by reasonable-size switched-capacitor circuits. Continuous-time /spl Sigma//spl Delta/ circuits have several serious problems, including high sensitivity to clock jitter, difficulty in filtering the output waveform, and extreme sensitivity to intersymbol interference in the pulse output waveform. These problems are reduced.

A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

An audio /spl Sigma//spl Delta/ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.

A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique

Previously reported multi-bit oversampling DeltaSigma audio DACs use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture.

A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique

A low power audio oversampling SigmaDelta digital-to-analog converter (DAC) with a three-level (+1, 0,-1) dynamic-element-matching (DEM) technique and an inter-symbol interference-free (ISI) output stage is presented. Solutions for design challenges such as ISI, clock jitter sensitivity, and out-of-band noise are presented. The converter is fabricated in a 0.18 mum CMOS process, occupies 0.55 mm2, achieves 108 dB dynamic range, -98 dB THD + N while consumes a total of 1.1 mW per channel at 1.8 V supply.

A 106dB SNR hybrid oversampling ADC for digital audio

A /spl Delta//spl Sigma/ ADC with a CT 1/sup st/-stage is presented. A hybrid tuning circuit adjusts the RC time constant to compensate for process, supply, and sampling rate variations. The ISI of the feedback DAC is eliminated by an RTZ scheme applied to the error current of the CT integrator. The ADC achieves 106dB SNR, -97dB THD+N, occupies 0.82mm/sup 2/ in a 0.35/spl mu/m CMOS process and dissipates 18mW.

A 113 dB SNR oversampling sigma-delta DAC for CD/DVD application

A sigma-delta (/spl Sigma//spl Delta/) audio digital-to-analog converter (DAC) for CD and digital versatile disk (DVD) application is presented. The converter uses a 6-bit modulator and a segmented noise-shaped scrambling technique to achieve a 113 dB dynamic-range over a 20 kHz bandwidth. A continuous-time output stage is used to achieve a high signal-to-noise (SNR) in a small die area. This output stage employs a dual return-to-zero scheme to eliminate errors caused by inter-symbol interference (ISI). The converter is fabricated in a 0.6 /spl mu/m double-poly double-metal CMOS process. The chip occupies 3.1/spl times/3.2 squared mm and operates from a single 5 V supply.

A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications

A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.