Kholdoun Torki

Low power hardware-based image compression solution for wireless camera sensor networks

In this paper, we present and evaluate a hardware solution for user-driven and packet loss tolerant image compression, especially designed to enable low power image compression and communication over wireless camera sensor networks (WCSNs). The proposed System-on-Chip is intended to be designed as a hardware coprocessor embedded in the camera sensor node. The goal is to relieve the node microcontroller of the image compression tasks and to achieve high-speed and low power image processing. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. We discuss in depth the internal hardware architecture of the encoder chip which is planned to reach high performance running in FPGAs and in ASIC circuits. Synthesis results and relevant performance comparisons with related works are presented. We study a low power hardware solution for image compression in wireless camera sensor network. The goal is to relieve the node microcontroller of the image compression tasks and to achieve low-power image processing. We discuss the internal hardware architecture of the proposed encoder circuit and its implementation. We provide relevant comparisons with related solutions.

Design and performance analysis of a zonal DCT-based image encoder for Wireless Camera Sensor Networks

Systems mapped on CMOS architectures are often expected to achieve high processing bandwidth and low energy consumption. However, a specific care should be paid to adequate the algorithm structure to the circuit architecture when designing multimedia wireless embedded networking systems. This paper addresses the problem of low power consumption and real time constraints for image communication in wireless camera sensor networks (WCSN). It presents a low-complexity hardware implementation of JPEG-like encoder for image compression and paquetization. The designed circuit is planned to be embedded in the camera sensor node to relieve the main processor of the data processing tasks. This encoder combines the best lifting DCT algorithm of the literature with a zonal coding approach. The former reduces the number of operations required per DCT coefficient while the latter reduces the number of coefficients to be computed, quantized and encoded. We study the tradeoff between the size of the zonal mask (a square zone of size k) and the visual image quality as a function of the compression bitrate, then we describe the hardware features of the JPEG-like circuit when implemented on different FPGAs and ASIC prototypes. Performance evaluation is provided for several ranges of compression bitrate, accordingly with the right value of k. Considering a grayscale image compressed to 0.25bpp for example, k=4 is the best choice. In this case, and for an image of 128x128 pixels, the CMOS circuit of the proposed encoder, synthesized using 45nm integration technology, clocks at 360MHz and consumes 18.02mW. It outperforms most of similar circuits being presented in the literature.

Digital hardware implementation of a neural network used for classification

In this paper, we propose a fully digital hardware implementation of neural networks. We describe the functioning of a digital artificial neuron and we propose a general architecture of a generic neural network. An example of a static neural network is given to show the efficiency of the implementation.

Efficient hardware solution for low power and adaptive image-compression in WSN

In this paper, we present and evaluate a hardware implementation for user-driven and packet-loss tolerant image compression, especially designed to enable low-power image compression and communication over wireless sensors networks (WSNs). The proposed compression scheme, presented as a CMOS circuit, is intended to be embedded in the camera sensor. It will be considered as a co-processor for tasks related with image compression and data packetization, which unloads the main microcontroller so that it will spend less time in active mode. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end-user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. The main part of this paper focuses on the specification and the performances analysis of this solution when implemented on FPGA and ASIC circuits.

Design of New Optimized Architecture Processor for DWT

This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in different frequency bands (octave bands). We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four filters, and a control unit. The filters are of different lengths and with new coefficients derived from Daubechies filter coefficients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12×106samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI.

A low-resource 32-bit datapath ECDSA design for embedded applications

In this paper we describe a hardware implementation of a low resource digital signature design using Elliptic Curve Digital Signature Algorithm (ECDSA). The implementation of ECDSA is based on the recommended GF (2163) NIST Elliptic Curve Cryptography (ECC). Elliptic curve based systems can be implemented with much smaller parameters, leading to significant performance advantages. Such performance improvements are particularly important for embedded applications where computing power, memory, and battery life of devices are more constrained. In order to meet these fierce constraints, our design has a 32bit word size. The design flow starts from an architectural description at the RTL level in order to interact easily with current commercial hardware synthesis tools. After simulation and synthesis steps, implementation is achieved on a Virtex-5 XC5FX70t FPGA using Xilinxs ISE design suite. Furthermore, the design was also implemented in both 65 nm and 40 nm CMOS ASIC design for performance comparisons. The Virtex-5 design requires 10838 slices with 1.58 ms (207.097 MHz) for signature generation and 12922 slices with 1.953 ms (195.309 MHz) for verification process. The ASIC design has an area of 467617 μm2 (726798 μm2) for signature generation and 260713μm2 (408350 μm2) for signature verification respectively using CMOS 65 nm and 40 nm technology. When running at a frequency of 500 MHz, the design consumes 2.71 mW (1.56 mW) of power for generation process and 3.90 mW (2.23 mW) for verification using a CMOS 65 nm and 40 nm technology respectively. From the implementation results, it is verified that the proposed ECDSA design are faster compared to literature with less power dissipation.

Communication synthesis techniques for multiprocessor systems

This paper presents an interactive communication synthesis approach for multiprocessor systems. The aim of the approach consists in mapping a high level specification into a modular and flexible target architecture. The input specification is composed of a set of finite state machines that communicate via a procedural call mechanism. If we assume that the communication critical part is done through a shared memory, this approach allows us to refine the communication structures (interfaces, controllers) in order to reach an operational model easily mappable onto the target architecture. While the choice of communication protocols influences what the best partition is, the target architecture is extendible in order to minimize the communication cost that can be added by the partitioning. The proposed approach is validated through the design of a communication controller.

TCP flow control technique for an interworking interface: hardware implementation

Abstract Current TCP flow control depends on packet losses to find the workload that a network can support. A variety of situations, including lossy wireless networks, asymmetric networks and web traffic workload, violates many of the assumptions made by TCP, causing degraded end-to-end performances. To improve the performance of TCP over heterogeneous networks (Ethernet and ATM interconnection), we propose a new technique, which we call Vegas–Snoop+, based on Vegas and Snoop protocols. Two modified service elements take part on the Vegas–Snoop+ technique. First, Vegas service element manages the connection parameters to achieve better throughput. Second, Snoop service element isolates the Ethernet senders from the characteristics of the ATM link. The objective in this paper is to win from advantages of Vegas and Snoop protocols, as well as to search an interconnection interface for networks interoperability. Actually, the development of two new integrated circuits (the BCM5680 (switch) and the BCM5401 (PHY)) orientate researchers to implement, at higher layer of the OSI model, flow control mechanisms to ensure reliability. Vegas–Snoop+ is an implementation of TCP, which gives in this way a solution for traffic management and congestion control improving good throughput with more reliability.

The design of MAC unit for DWT implementation

High performance FIR filters have applications in several video processing and digital communications systems. Audio and telecommunication applications may use filters at sample rates of 10-30 MHz. High-speed digital data communications or high rate video transmission systems may need preferment filters. This paper deals with the VLSI implementation of a recursive filter. The designed device will he used as a sub-element for the design of a DWT circuit. The performance of the DWT circuit depend on the performance of the MAC unit.

Performance Evaluation of MIC@R NoC for Real-Time Applications

The smart electronic homes evolution is strongly related to the System-on-Chip (SoC) development. This, in turn, requires an efficient intercommunication between its Intellectuals Proprieties (IPs). Network-on-Chip (NoC) represents the suitable solution. This paper presents a design and implementation of MIC@R NoC architecture performed with non-uniform traffics. This architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed NoC architecture is implemented in ASIC technology and performed in 2D mesh networks. In this paper we present a study of NoC evaluation. This NoC uses the four routing algorithms: Deterministic X-Y, Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Proximity Hot-Spot Awareness (PHSA). The PHSA scheme is a novel routing technique proposition that is more efficient than the other ones. NoC performance evolution is measured with non-uniform traffics that are hot-spot and transpose patterns. Obtained results show that MIC@R router combined with proposed routing techniques is efficient in terms of low latency and generic aspect.