Khyoupin Khoo

Effect of the Purity of Plating Materials on the Reduction of Resistivity of Cu wires for Future LSIs

Resistivity difference between Cu wires made with plating using high purity (new plating process) and conventional purity (conventional process) materials has been evaluated in order to develop the process for the realization of high performance LSIs. This resistivity difference is relatively small, i.e., 8% when line width is wide (200 nm). However, it increases with the decrease in line width, and it reaches about 20%, i.e., 2.8 μΩ cm for the former and 3.5 μΩ cm for the latter at 50 nm line width. A 50 nm wide Cu wire formed with the new plating process had more uniform and larger grain sizes and lower impurity concentrations than the wire formed with the conventional process.

Observation of microstructures in the longitudinal direction of very narrow Cu interconnects

We have succeeded in observing the longitudinal microstructure of very narrow Cu interconnects for the first time. We found that the average grain sizes along the longitudinal direction of Cu interconnect trenches increased with increasing line width, and they were 278 nm for 80 nm, 303 nm for 100 nm, and 346 nm for 180 nm wide interconnects. Ratios of the average grain size to line width were 3.5 for 80 nm, 3.03 for 100 nm, and 1.9 for 180 nm line widths.

Reduction in resistivity of 50 nm wide Cu wire by high heating rate and short time annealing utilizing misorientation energy

The resistivities and microstructures for 50 nm Cu wires fabricated by high heating rate (3 K/s) and short time (1 min) annealing using infrared rapid thermal annealing equipment have been investigated as a function of annealing temperature and compared to those properties for wires fabricated by a slow heating rate (0.08 K/s), long time (30 min) conventional H2 annealing process. The resistivity of wires annealed by the new process decreased substantially with increasing annealing temperature from 573 to 773 K. The resistivity had its lowest value between 773 and 873 K, and it increased rapidly with annealing temperature above 923 K. The average ρ value was 2.98 μΩ cm for 773 K new process wires, whereas average ρ values were about 3.55 μΩ cm for 573 K and 3.42 μΩ cm for 673 K conventionally H2 annealed wires. This resistivity value for the new process wires was about 16% lower than the value for wires annealed at 573 K and 13% lower than the value for the wires annealed at 673 K by the conventional H2 a...

The Development of an Innovative Process of Large Grained and Low Resistivity Cu Wires for less than hp 45nm ULSI

We have developed an innovative process to create large grained and low resistivity Cu wires for less than hp 45 nm ULSIs. The resistivity of the 50 nm wide Cu wires by an innovative high purity process is found to be 21% lower than those created by the conventional process. It was also found that Cu wires formed with the new high purity process have larger grains with a smaller spread and a lower impurity concentration than those made with the conventional process. This innovative new process is expected to be a powerful candidate for created Cu wire of less than hp 45 nm ULSIs.

Aspect Ratio Dependence of the Resistivity of Fine Line Cu Interconnects

The effect of aspect-ratios of very narrow Cu interconnects of less than 100 nm on the resistivity has been discussed. From longitudinal cross-sectional transmission electron microscope (TEM) observation, many very small grains were observed at the bottom of the trench, while larger grain sizes are predominant in the upper part of the Cu interconnects. The resistivity was found to decrease significantly when increasing the aspect-ratio in fine line Cu wires due to the larger grain size distributions in the upper part of the Cu interconnects with higher aspect-ratios. This result demonstrates that the aspect-ratio of Cu wires are effective for controlling the resistivity in future Cu interconnects with very narrow and shallow dimensions.

Filling 80-nm-Wide and High-Aspect-Ratio Trench with Pulse Wave Copper Electroplating and Observation of the Microstructure

To completely fill 80-nm-wide trenches with high-aspect-ratio (>6) Cu electroplating, we investigated the influence of pulse wave electroplating conditions. Peak current density and current-off time during pulse wave plating were found to affect bottom-up filling. Bottom-up filling was confirmed to occur when peak current density, current-on time and current-off time were 100 mA/cm2, 3 and 300 ms, respectively. The microstructure of the trench was observed before and after annealing at 673 K by transmission electron microscope. After annealing, the grain size increases and grains cross the trench width. The size of grains formed by pulse wave plating before and after annealing were 37.5 and 96 nm, respectively. These values were similar to those for DC plating. Pulse wave electroplating is, therefore, promising as a step in the dual damascene process for fabricating very narrow high-aspect-ratio Cu wiring.