Jin Onuki

Effect of the Purity of Plating Materials on the Reduction of Resistivity of Cu wires for Future LSIs

Resistivity difference between Cu wires made with plating using high purity (new plating process) and conventional purity (conventional process) materials has been evaluated in order to develop the process for the realization of high performance LSIs. This resistivity difference is relatively small, i.e., 8% when line width is wide (200 nm). However, it increases with the decrease in line width, and it reaches about 20%, i.e., 2.8 μΩ cm for the former and 3.5 μΩ cm for the latter at 50 nm line width. A 50 nm wide Cu wire formed with the new plating process had more uniform and larger grain sizes and lower impurity concentrations than the wire formed with the conventional process.

Observation of microstructures in the longitudinal direction of very narrow Cu interconnects

We have succeeded in observing the longitudinal microstructure of very narrow Cu interconnects for the first time. We found that the average grain sizes along the longitudinal direction of Cu interconnect trenches increased with increasing line width, and they were 278 nm for 80 nm, 303 nm for 100 nm, and 346 nm for 180 nm wide interconnects. Ratios of the average grain size to line width were 3.5 for 80 nm, 3.03 for 100 nm, and 1.9 for 180 nm line widths.

A Void Free Soldering Process in Large-Area, High Power Insulated Gate Bipolar Transistor Modules

We have developed a new void free process for making the solder joint between the chip mounted AlN substrate and the metal substrate in large-area, high power insulated gate bipolar transistor (IGBT) modules. This new process consists of two steps. First, Ar+ were used to clean the surfaces of Ni plated film on a metal and AlN substrates which were then coated with 0.5-µm-thick Ag film. Second, 50 wt% Pb–Sn solder was sandwiched between the two substrates and heated to 503 K in a vacuum for 5 min before being cooled in a N2 atmosphere. By using this process, the area percentage of voids in a soldering area up to 130×190 mm2 can be reduced to less than 0.1%. IGBT modules made by this process were also found to exhibit satisfactory current-voltage characteristics.

Reduction in resistivity of 50 nm wide Cu wire by high heating rate and short time annealing utilizing misorientation energy

The resistivities and microstructures for 50 nm Cu wires fabricated by high heating rate (3 K/s) and short time (1 min) annealing using infrared rapid thermal annealing equipment have been investigated as a function of annealing temperature and compared to those properties for wires fabricated by a slow heating rate (0.08 K/s), long time (30 min) conventional H2 annealing process. The resistivity of wires annealed by the new process decreased substantially with increasing annealing temperature from 573 to 773 K. The resistivity had its lowest value between 773 and 873 K, and it increased rapidly with annealing temperature above 923 K. The average ρ value was 2.98 μΩ cm for 773 K new process wires, whereas average ρ values were about 3.55 μΩ cm for 573 K and 3.42 μΩ cm for 673 K conventionally H2 annealed wires. This resistivity value for the new process wires was about 16% lower than the value for wires annealed at 573 K and 13% lower than the value for the wires annealed at 673 K by the conventional H2 a...

Development of high-reliability thick Al-Mg 2 Si wire bonds for high-power modules

Durability of IGBT modules mainly depends on reliability of the thick Al wire bonds used in them. We investigated the reliability of thick Al-0.5mass%Mg2Si wire bonds in comparison with conventional Al-50ppm Ni wire bonds. The shear strength of both Al-0.5mass%Mg2Si and Al-50ppmNi wire bonds were measured as a function of the number of thermal cycle tests. The strength ratio of Al-50ppmNi wire bonds decreased substantially with the number of cycles and it was 78.8% of the original strength after 10,000 cycles. On the other hand, that of Al-0.5mass%Mg2Si wire bonds was almost unchanged after 10,000 cycles. Degradation ratios of Al-0.5mass%Mg2Si and Al-50ppm Ni wire bonds at 10,000 cycles were about 1.6% and 21.2%, respectively; thus reliability of the former was ten times larger than that for the latter.

Effect of Physical Properties of Al–Si Electrode Films on the Deformation Behaviors and the Strength of Thick Al Wire Bonds during Thermal Cycle Test

The deformation behaviors of Al–Si films and the strength change of Al wire bonds on Al–Si films during heating and cooling cycles have been investigated as a function of substrate temperature of the sputtering process; the purpose was to clarify reliability of both Al wire bonds and Al–Si films for use in insulated gate bipolar transistor (IGBT) modules. The extent of deformation in Al–Si films sputtered at 593 K during heating and cooling cycles was the smallest among films sputtered at room temperature (RT), 473 K, and 593 K. The strength of Al wire bonds on Al–Si films sputtered at the three temperatures was the highest for Al–Si films sputtered at 593 K. The reliability of Al wire bonds on Al–Si films formed at 593 K was about two times higher than the bond reliability on Al–Si films formed at RT and 473 K.

The Development of an Innovative Process of Large Grained and Low Resistivity Cu Wires for less than hp 45nm ULSI

We have developed an innovative process to create large grained and low resistivity Cu wires for less than hp 45 nm ULSIs. The resistivity of the 50 nm wide Cu wires by an innovative high purity process is found to be 21% lower than those created by the conventional process. It was also found that Cu wires formed with the new high purity process have larger grains with a smaller spread and a lower impurity concentration than those made with the conventional process. This innovative new process is expected to be a powerful candidate for created Cu wire of less than hp 45 nm ULSIs.

Aspect Ratio Dependence of the Resistivity of Fine Line Cu Interconnects

The effect of aspect-ratios of very narrow Cu interconnects of less than 100 nm on the resistivity has been discussed. From longitudinal cross-sectional transmission electron microscope (TEM) observation, many very small grains were observed at the bottom of the trench, while larger grain sizes are predominant in the upper part of the Cu interconnects. The resistivity was found to decrease significantly when increasing the aspect-ratio in fine line Cu wires due to the larger grain size distributions in the upper part of the Cu interconnects with higher aspect-ratios. This result demonstrates that the aspect-ratio of Cu wires are effective for controlling the resistivity in future Cu interconnects with very narrow and shallow dimensions.

Purification of CuCl2 by Anion Exchange Separation using Multi-column Method

The demand for high purity Cu is growing because it has an advantage to reduce the resistivity of the interconnect in ultra large-scale integration. Anion-exchange separation with the multi-column method was proposed and its separation efficiency was investigated in this work. The recoveries of anion-exchange separation for Cu purification in the previous studies are relatively low. Whole separation efficiency would be improved if the yield could be increased. Prior to the separation tests, the target impurities were determined from thermodynamic consideration of the process for preparation of high purity Cu. As a result, anion-exchange separation with the multi-column method proposed in this paper successfully eliminated the possible impurities, which should be removed in order to obtain a ultra high purity Cu. Thus, the purified CuCl 2 -HCl solution is ready for preparation of the ultra high purity Cu. *To whom correspondence should be addressed +IMRAM, Tohoku University, Japan J Graduate Student, Tohoku University, Japan ^College of Engineering, Ibaraki University, Japan

Void generation during the annealing process of very narrow copper wires

We carried out experiments on stress-induced void formation in ultrathin Cu wires while varying heat-treatment temperature, wire dimensions, and overlayer thickness. We also did molecular dynamics simulations of void formation in a buried wire of nanometer scale and compared these results with experimental results to clarify details of the void formation mechanism. The experimental and simulation results showed good accordance in explaining the effects of wire width, overlayer thickness, and cooling rate on void formation. (1) The narrower the wire width, the easier the void formation. (2) The thicker the overlayer, the easier the void formation. (3) The larger the cooling rate, the greater the suppression of void formation. From the obtained results, we constructed a void formation model for a buried wire. The basic concept of the model describes how local strain at four trench corners is relaxed in the buried wire in the annealing process. There are two ways to relax the local strain: (1) structural rel...