Ki-Sang Lee

Observation of Micro-Oxygen Precipitates in the Vicinity of the Oxidation-Induced Stacking Fault Ring and Their Effects on Thin Gate Oxide Breakdown

Micro-oxygen precipitates and their effects on thin gate oxide breakdown have been investigated using a crystal-originated-particle (COP)-free wafer and a low COP wafer. After two-step annealing and subsequent repolishing, regions containing micro-oxygen precipitates were observed inside and outside the oxidation-induced stacking fault (OSF) ring. Delta [Oi] and near-surface microdefects (NSMDs) in those regions showed a reverse trend. It appears that micro-oxygen precipitates show a different precipitation behavior from the anomalous oxygen precipitation (AOP) behavior in the conventional Czochralski (CZ) silicon wafer with the OSF ring. The oxide breakdown electrical field was degraded in almost the same region as that where micro-oxygen precipitates were revealed. This indicates that micro-oxygen precipitates can affect the degradation of gate oxide integrity (GOI).

Effects of surface roughness and copper contamination on the oxide breakdown of silicon wafer

Surface roughness of silicon wafer was increased by the immersion in NH4OH solution. And copper contamination was applied to rough surface. Current–voltage characteristics were measured on 12 nm oxide. The rates of dielectric breakdown were increased consistently following the increase of roughness and copper contamination. In Fowler–Nordheim tunneling regime, abnormal current variations such as shift and hump were observed. By the tunneling current analysis, each contribution of roughness and copper contamination was related to two kinds of current variation. The shift of tunneling regime to lower electric field was induced by surface roughness via the increase of effective interface area. And the deformation in tunneling characteristics was attributed to copper contamination via the decrease of effective oxide thickness.

Failure Mechanism by Organic Contaminants in Si Device Fabrication

Organic contaminants are particularly more difficult to classify or control than the others such as metal impurities or particulate matters because of their ubiquitous contamination from all sources of manufacturing facilities. Especially, bis(2-ethylhexyl) phthalate (DOP) used as plasticizer is shown to be an indicator of organic contamination because of its nonor low volatility and strong adsorption onto the silicon wafer. 2 We used DOP for quantitatively contaminating the wafer surface and studied its effects. Contaminated DOP spots were almost completely removed from the wafer surface during thermal oxidation of silicon. However, a very small portion of the spots remained on the surface and captured in the interface between polysilicon and silicon oxide layers during the polysilicon deposition process as schematically shown in Fig. 1. Fig. 2 shows the results of current vs. electric field (I/EF) measurements after the gate oxidation processing on a wafer. In the reference sample, large leakage currents of about 1x10 A/cm are observed only at the electric field of higher than 12 MV/cm and the increases in current begin to level off beyond about 7 MV/cm. On the other hand, the threshold EF values, at which currents begin to increase, shift to increasingly smaller values and rapid increases in current upon small increase in the electric field start to show up as the currents get close to the saturated values when the initial DOP concentration is increased. The decrease in slope just before breakdown voltage (BV) indicates that the resistance increases due to the thicker silicon oxide layers. However, the decrease in the BV suggests that the interface breaks down at a lower electric field resulting in an increase in leakage current due most likely to the presence of more conducting substance than the silicon oxide at the interface. To address how these contaminants induce the device failures, we show the cross-sectional views of the TEM images on the failed cells for the varied initial DOP concentrations in Fig. 2. The thickness of the silicon oxide layer, which was supposed to have grown to 80 A (= 8 nm), was increased from 8 nm to 13, 31 and 32 nm upon contaminating the surface by increasing the initial DOP surface concentration from 0 to 5x10 molecules/cm although the thermal oxidation of the silicon surface was carried out for the same duration in a furnace under identical experimental conditions. It is conceivable that the organic compounds may be reduced to elemental carbon in the presence of large amounts of silicon oxide at high temperature of 800C. The elemental carbon would then serve as a current leakage site, through which the current begins to flow and facilitates the breakdown of the interface. We have shown clearly that the organic contaminants are trapped during the thermal oxidation processing of silicon, which provide various routes to device failures; a portion of the organic contaminants remaining as the carbon compounds induces the expansion of the silicon oxide lattice, deteriorating the silicon oxide layer, resulting in the device failure. Results of our study clearly provide reasons for why the facilities for device fabrication must be kept extremely clean and the polymers using high concentrations of plasticizers should be avoided as much as possible from the clean room environments.

Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness

The dielectric breakdown of oxides with various thickness between 5–70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX range of 10–20 nm. On the other hand, COP-free wafers showed few breakdowns over all the range of tOX. Furthermore, time dependent dielectric breakdown (TDDB) of the vacancy-rich wafers showed higher extrinsic breakdowns than that of the COP-free wafers in the tOX below 20 nm. For the intrinsic breakdown, two groups showed the same charge-to-breakdown (QBD) along the strength of injection current over all the range of tOX. Especially, only in case of vacancy-rich wafer, abnormal increase of current, i.e., hump phenomena, was observed in the range of electric field below the Fowler-Nordheim (F-N) tunneling.