Hee-Bok Kang

An EPC Gen 2 compatible passive/semi-active UHF RFID transponder with embedded FeRAM and temperature sensor

A fully integrated passive and battery powered semi-active UHF RFID transponder chip supporting EPC Gen 2 protocol is presented. The proposed transponder works as a passive RFID tag when the generated RF-power is sufficient to operate, otherwise it operates in semi-active mode using battery power. The chip has re-writeable non-volatile memory bank formed by FeRAM and on-chip temperature sensor. The memory consists of EPC memory bank for EPC functionality and temperature bank for storing sensed data. The standby current in semi-active is about 0.5 muA, the lifetime in semi-active mode is in excess of 2 year with a 10 mA-hr thin film battery.

Programming disturbance and cell scaling in phase change memory: For up to 16nm based 4F 2 cell

We focus here on the promising solutions to overcome thermal-induced erase failure of the unselected neighbor cell while a selected cell is being programmed to reset state with a high-current pulse. Our physical analysis directly demonstrate that this parasitic heating in Ge2Sb2Te5 based cell leads to partial crystallization in the amorphous reset state and to a consequent resistance decrease with disturbing current. Systematic approaches compatible with disturbance-free are addressed to achieve a highly scalable architecture, which can provide the physical and electrical criteria for phase change memory (PCM) up to 16nm technology node.

Performance and Reliability of Low-Temperature Processed SrBi2Ta2 O 9 Capacitors for FeRAM Applications

Low-temperature processed SrBi 2 Ta 2 O 9 (SBT) capacitors were tested as the ferroelectric memory cells of fully functional ferroelectric random access memory (FeRAM) devices. The 100 nm thick SBT films were deposited by the spin-on coating technique using a metallorganic decomposition source and crystallized by rapid thermal annealing at 700°C for 1 min followed by a furnace annealing at 650°C for I h under oxygen atmosphere, considered a low thermal budget process. The fabricated Pt/SBT/Pt capacitors showed reasonable ferroelectric performances with a AP (switching polarization-nonswitching polarization) of approximately 10 μC/cm 2 after the full process integration. The FeRAM chip-level reliability analysis showed that the major reason for the function failure was from the opposite state retention characteristics due mainly to the small AP values. A 10-year guaranteed lifetime can be achieved when the operation voltage is higher than approximately 4 V at the test condition of 85°C operation and 125°C storage.

Integration of a split word line ferroelectric memory using a novel etching technology

Abstract A ferroelectric random access memory (FeRAM) was fabricated using a novel processing technology to investigate the characteristics of the FeRAM with a new cell structure. The new cell includes two split word lines (SWLs) which play roles not only as word lines but also as plate lines. This structure can enhance operation speed and prevent the decrease of remnant polarization of non-selected cell capacitors in write/read operation since SWLs can be driven independently. The cell capacitors were composed of Pt electrodes and the sol-gel derived Pb(Zr,Ti)O3 films. An efficient procedure to realize the new cell structure is proposed by introducing a new etching method, which includes the one-step patterning of a metal-ferroelectric-metal (MFM) and a metal-ferroelectric (MF) using a metal mask (Ti or Ru) and an etch stopping layer (TiO2 or RuO2). The degradation of the ferroelectric capacitors due to etching process and interlayer dielectric (ILD) deposition process was almost recovered by annealing...

Core Circuit Technologies for PN-Diode-Cell PRAM

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90㎚ technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM

This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.

Quantitative Evaluation of Gettering Efficiencies Below 1 × 1012 Atoms ∕ cm3 in p-Type Silicon Using a #2#1 Tracer

Gettering efficiencies of copper, whose bulk concentrations are lower than 1 X 10 12 atoms/cm 3 in p-type silicon, have been evaluated quantitatively and the results are reported. Bulk copper introduced by intentional spiking and subsequent heat-treatment was shown to be gettered by bulk microdefects (BMDs), which had been introduced by heat-treatment prior to intentional contamination using a 65 Cu isotope tracer as a probe. For evaluation of gettering efficiencies, we found the trace analysis of the 65 Cu isotope to be critical and, thus, developed a procedure for trace analysis of bulk copper in the silicon bulk by modifying the published analytical technique, which allowed gettering efficiencies to be quantitatively evaluated for copper levels of below 10 12 atoms/cm 3 . We also describe a few other parameters important to the evaluation of gettering efficiencies, including out-diffusion of copper through the silicon matrix, formation of BMDs, and low-temperature out-diffusion.

Issues and Reliability of High-Density FeRAMs

We discuss some technical issues on the realization of high-density ferroelectric random access memory (FeRAM). Due to reliability concerns of ferroelectric materials, such as fatigue, retention, and imprint, an extra sensing margin is required. In order to overcome these drawbacks, we have improved the ferroelectric capacitor process and design architecture. The fatigue and imprint degradations of the ferroelectric capacitor are significantly suppressed using the newly developed (Bi1-xLax)4Ti3O12 (BLT) films. The design architecture was improved using the split word line (SWL) cell array and current gain cell (CGC) operation. Using the above BLT capacitors and design architectures, we have obtained a high sensing margin, a high cell efficiency, and a small cross-talk noise in high-density FeRAMs.

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

A Current-Gain Scheme for High Density and Low Voltage FeRAM

The proposed current-gain scheme provides a key technical solution for a high density, low cost and high performance ferroelectric random access memory. The proposed sensing scheme shows maximum sensing-signal window because of divided sub-bitline (SBL) structure. The unit cell array section is composed of the cell array of 64 rows and 128 columns with SBL, SBL switch (SBSW) devices and current-gain transistor (CGT) device. The global main bitline (MBL) is biased by MBL sensing load (MSL) device and connected to common MBL bus (CMB) through block selection switch (BSS) device. The device sizes of CGT and MSL devices are key factors for determining the transfer characteristics of SBL and MBL. The 128 sense amplifiers in peripheral circuit region are shared to all cell array blocks through CMB with 128 MBL columns of each cell array block. The address access time of the 16 Mb chip is evaluated to less than 70 ns at 3 V.