Keum-Hwan Noh

Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies

Our Middle-1X nm MLC NAND (M1X) flash cell is intensively characterized with respect to reliability and manufacturability. For the first time, the novel active air-gap technology is applied to alleviate the drop of channel boosting potential of program inhibition mode, BL-BL interference is reduced to our 2y nm node level by this novel integration technology. Furthermore, it also relaxes the effect of process variation like EFH (Effective Field oxide Height) on cell Vt distribution. Better endurance and retention characteristics can be obtained by p+ doped poly gate. By optimization of active air-gap profile and poly doping level, M1X nm MLC NAND flash memory has been successfully implemented with superior manufacturability and acceptable reliability.

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

A 16 Mb 1TIC FeRAM with a novel cell structure has been successfully developed with 0.25 /spl mu/m process technology using (Bi,La)/sub 4/Ti/sub 3/O/sub 12/ (BLT) capacitors for the first time. The developed FeRAM is highly scalable and reliable as a result of applying an MTP (merged top electrode and plate line) structure and BLT stacked capacitor, respectively.

Retention properties of fully integrated (Bi,La)4Ti3O12 capacitors and their lateral size effects

We investigated the retention characteristics of (Bi,La)4Ti3O12 (BLT) capacitors and their lateral size effects in a fully integrated device structure. Unlike the commonly used Pb(Zr,Ti)O3 capacitors for ferroelectric random access memories (FeRAMs), which have poor opposite-state retention characteristics, BLT capacitors showed very stable characteristics in both the same- and the opposite-state retention tests. These good retention properties were closely related to the small amount of imprint in the BLT capacitors. In addition, the retention characteristics of BLT capacitors showed no practical degradation due to the size reduction, down to 0.49×0.64μm2, which could be used for highly integrated FeRAMs of 32MB density.

Impurities in dielectrics and hydrogen barriers for SrBi2Ta2O9-based ferroelectric memories

We report results of systematic investigation of impurities in dielectrics and hydrogen barriers (Ti and Al2O3 films) during the integration process of SrBi2Ta2O9-based ferroelectric memories. The capacitors integrated with Ti hydrogen barriers are not electrically degraded regardless of the annealing conditions of the subdielectrics. On the contrary, electrical properties of the capacitors using Al2O3 hydrogen barriers significantly depend on the annealing temperatures for subdielectrics. It turned out that interaction of the dielectrics with plasma during sputtering of the Ti films caused fragmentation of the moisture in the dielectrics and absorption of the hydrogen in the Ti films, making annealing irrelevant. However, the alumina films blocked both hydrogen and moisture in the subdielectrics during the passivation process, resulting in dependence on the annealing temperatures.

Highly reliable 1 Mbit ferroelectric memories with newly developed BLT thin films and steady integration schemes

Highly reliable packaged 1 Mbit ferroelectric memories with 0.35 /spl mu/m CMOS ensuring ten-year retention and imprint at 175/spl deg/C have been successfully developed for the first time. These excellent reliabilities have resulted from newly developed BLT ferroelectric films with superior performance and steady integration schemes free from attacks of process impurities.

Imprint Characteristics of Bi-Layered Perovskite Ferroelectric Thin Films

The imprint characteristics of SrBi2Ta2O9, SBT, and (Bi0.8La0.2)4Ti3O12, BLT, thin film capacitors have been evaluated at the storage temperature of 125 □. The coercive voltage shift and the polarization loss occurred as a function of the logarithmic storage time. BLT capacitors showed more stable imprint characteristics than SBT. The increasing rate of the coercive voltage shift and the decreasing rate of the polarization loss of BLT with a storage time were smaller than that of SBT. The BL sensing signals were measured on 2T2C-256 Kbits FeRAM adopted SBT and BLT capacitor in order to estimate the imprint life times of the devices, respectively.

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

Characterization of Hynix 16M Feram Adopted Novel Sensing Scheme

16M FeRAM was successfully developed using a (Bi1 − X La X )4Ti3O12, BLT, film with excellent imprint characteristic as a ferroelectric film to decrease capacitor size, current gain cell operation (CGCO) sensing scheme, and split word line (SWL) cell array architecture with hierarchical-double bit line in order to increase cell array efficiency. The chip size of 16M FeRAM could be reduced down to about 63% compared with a conventional one by the adoption of the novel ferroelectric material and the design architectures. The read/write access time and cycle time are 70 ns and 100 ns in operation voltage of 3.0 at room temperature, respectively. The operation and standby current are less than 20 mA and 10 μA, respectively.

Gate Annealing of Cycling Endurance and Interface States for Highly Reliable Flash Memory

We report on superior cycling endurance due to a low interface trap density, which accounts for the high gate annealing temperature in flash memory. The interface trap density was characterized using a charge pumping method (CPM). The cycling VTH shift in an erase state value of 1.35 V at 850 °C temperature of an annealing, as measured on a 90-nm-technology 1-Mbit cell array, selected randomly from 1 Gbit cells, drops to less than 0.9 V after annealing at 950 °C. These superior electrical properties resulted from a complete relaxation of silicon interface trap charges due to a plasma-induced attack during gate annealing at temperatures over 950 °C for a long time. Therefore, the key factor for highly reliable endurance with cycling is believed to be the interface trap control of the thermal annealing carried out after gate etching.

A CELL MODEL FOR NON-VOLATILE RANDOM ACCESS MEMORY AND A SUBSEQUENT METHOD FOR INCREASING DENSITY

ABSTRACT A cell model for non-volatile random access memory (RAM) is suggested in this study. An indicator, a cell, was introduced to simplify the explanation. If the indicator is good, then the device to which it belongs is acceptable. An inequality acquired through modeling a cell can determine whether a cell is good or not. To satisfy the pass condition, the energy barrier for storage (Eb), the sum of uniformities (uniformity of non-volatile material (Ui), uniformity related to the relative position of a data cell and a reference cell (Us)), and the sensing signal margin (Vsm) must be high. The inequality means that eEbUieEbUs Vsm is larger than a constant. If the parameters of an indicator satisfy the inequality condition, the device will be acceptable. As any general property of the cell changes, the indicators property will also change accordingly. As cell density increases, inequality will not be satisfied due to decreasing Ui. A new cell that can be predicted with the model is suggested. Increasing Eb for data storage and decreasing Eb for data transition seems to be necessary to increase the cell density of non-volatile RAM. Eb of non-volatile material is controlled by metallic lines in a new cell.