Ki-Young Yun

TSV optimization for BEOL interconnection in logic process

Control of Cu extrusion and delamination due to CTE mismatch between Si and Cu is a big issue for high reliable TSV formation. In this paper we tried to find some methods to reduce Cu extrusion and to prevent TSV sidewall delamination. It is demonstrated that residual Cu extrusion height can be reduced by additional high temperature heat treatment before TSV CMP. And also Cu extrusion and delamination strongly depends on TSV dimension, which leads to the conclusion that smaller vias are preferred for better reliability.

Impact of TSV proximity on 45nm CMOS devices in wafer level

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using ‘via middle’ process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.

Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

Development of New Batch-Type Plasma Assisted NOR (Native-Oxide-Removal) Dry Cleaning Equipment

Introduction The more accumulative electronic devices are required, the smaller features, whose smallest size is measured by lithography half-pitch, should be achieved for semiconductor fabrication. Unexpected design and fabrication difficulties should be also overcome as devices shrink. One of difficulties is contact resistance by unforeseen insulation native oxide layers in junction areas. An even so thin native oxide layer may make contact resistance drastically higher and therefore brings about VLSI chip operation fails. Other problems by native oxide include current leakage at gate oxide and insufficient silicide formation on a device. To resolve these issues, surface cleaning process becomes very critical to make super-clean silicon surface on contact areas and thus semiconductor industry has developed various native oxide removal methods to obtain better chip productivity. We, in this paper, present a new and more effective cleaning way by an efficient batch type apparatus with a dry process to achieve super-clean silicon surface on very small contact holes of semiconductor chips.