Kian Paau Gan

Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices

The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance requirement and inter-diffusion problem. We report a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that requires the well-established oxide thickness control instead of the difficult doping control in translating the limit to a higher blocking voltage. This is done by using metal-thick-oxide (MTO) at the sidewalls of drift region. One can choose to have a higher blocking voltage or increase the background doping. A PiN structure, essentially identical to MOSFET during off state, was fabricated to demonstrate the proposed concept. Its measured BV/sub dss/ of 170 V is 2.5 times higher than measured conventional device BV/sub dss/ of 67 V on the same silicon wafer.

120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit

A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R/sub on, sp/ /spl prop/ BV/sub dss//sup 2.5/). The concept is based on replacing LDMOS lightly doped n-drift region by moderately doped alternating p and n layers of suitable dimension and doping. Off state requirement is achieved by mutual lateral-depletion of the alternating layers. Using small identical lateral width for both p and n layers, a doping concentration of up to two orders of magnitude higher than n-drift concentration in a conventional case can he achieved to reduce the on-resistance R/sub on/. The simulated 120 V IDLDMOS on SOI substrate has shown a R/sub on/ value that is about 38% of the corresponding R/sub on/ value of a conventional n/sup -/ LDD type LDMOS. At a R/sub on, sp/ value of 1.15 m/spl Omega/-cm/sup 2/ with BV/sub dss/ of 124 V, IDLDMOS has exceeded the conventional LDMOS limit. Compared to conventional LDMOS, IDLDMOS is less prone to quasisaturation at high gate and drain voltage due to its higher drain doping. Isothermal simulation has shown that there was no deterioration in both AC and transient performance between the two devices. Nevertheless, the lower V/sub d, sat/ of LDLDMOS is expected to yield a higher g/sub m/ at the same level of current conduction as in the conventional structure.

A simple technology for superjunction device fabrication: polyflanked VDMOSFET

The charge compensation based novel superjunction (SJ) MOSFET outperforms its conventional counterparts. However, the production of SJ devices is limited by a complicated and costly fabrication process. In this letter, a feasible technology for polyflanked vertical double-diffused MOS SJ structure, as in Gan et al. (2001), is introduced and demonstrated to have greatly reduced fabrication costs, simplified processes, and overcome the interdiffusion problem of SJ columns. This brings forth the new milestone that SJ MOS devices can now be fabricated by standard cleanroom facilities.

Tunable oxide-bypassed VDMOS (OBVDMOS): breaking the silicon limit for the second generation

The research effort to lower the on-state resistance for high voltage MOSFET devices continues. We have recently reported a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that utilized the well-established oxide thickness control instead of the difficult doping control in translating the on-resistance (R/sub on/) - blocking voltage (BV/sub dss/) tradeoff limit beyond the conventional MOSFET silicon limit. Further enhancement on both breakdown voltage and on-resistance can be achieved by applying an external bias to the poly contact of the device. Moreover, this bias provides an independent control of adjusting breakdown voltage if it does not meet specifications due to foundry process variations.

Poly flanked VDMOS (PFVDMOS): a superior technology for superjunction devices

A novel VDMOS structure, named poly flanked VDMOS (PFVDMOS), is proposed for the first time to provide a better performance and process technology for superjunction MOSFET devices. The structure contains a thin oxide barrier to eliminate the existing p-n lateral interdiffusion problem, thus both the n-epi and p poly column widths can be reduced to a minimum. This reduction in column width enables the device to have a much higher n-epi doping concentration. In a sense, it leads to an optimal reduction in on-state resistance compared to other existing structures for the same voltage rating.