Ganesh S. Samudra

Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric

Highly reliable characterization of fast transient in NBTI is achieved by performing initial and stressed I-V measurements in ultra-short time (100 ns). We further provide evidences that reaction-diffusion (R-D) model can not explain the fast transient in NBTI, while hole trapping (HT) model explains all experimental observations. We also establish that previous on-the-fly methods are sound except for the slow initial measurement. This caused the apparent disagreements among results from different groups using on-the-fly methods, which is resolved in this work by the fast on-the-fly technique

Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO high-/spl kappa/tunneling and control oxides: Device fabrication and electrical performance

We fabricated a nonvolatile Flash memory device using Ge nanocrystals (NCs) floating-gate (FG)-embedded in HfAlO high-/spl kappa/ tunneling/control oxides. Process compatibility and memory operation of the device were investigated. Results show that Ge-NC have good thermal stability in the HfAlO matrix as indicated by the negative Gibbs free energy changes for both reactions of GeO/sub 2/+Hf/spl rarr/HfO/sub 2/+Ge and 3GeO/sub 2/+4Al/spl rarr/2Al/sub 2/O/sub 3/+3Ge. This stability implies that the fabricated structure can be compatible with the standard CMOS process with the ability to sustain source-drain activation anneal temperatures. Compared with Si-NC embedded in HfO/sub 2/, Ge-NC embedded in HfAlO can provide more electron traps, thereby enlarging the memory window. It is also shown that this structure can achieve a low programming voltage of 6-7 V for fast programming, a long charge retention time of ten years maintaining a 0.7-V memory window, and good endurance characteristics of up to 10/sup 6/ rewrite cycles. This paper shows that the Ge-NC embedded in HfAlO is a promising candidate for further scaling of FG Flash memory devices.

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The strained N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of SiC in the S/D regions. The carbon mole fraction incorporated is 1.3%. Lattice mismatch of /spl sim/0.65% between SiC and Si results in horizontal tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The conduction band offset /spl Delta/E/sub c/ between the SiC source and the strained-Si channel also contributes to increased electron injection velocity from the source. Implementation of the SiC stressors provides significant drive current I/sub DS/ enhancement in the N-MOSFETs. I/sub DS/ enhancement of 50% was observed for a gate length of 50 nm.

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component exx and the vertical strain component ezz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-...

Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET ar...

Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices

The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance requirement and inter-diffusion problem. We report a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that requires the well-established oxide thickness control instead of the difficult doping control in translating the limit to a higher blocking voltage. This is done by using metal-thick-oxide (MTO) at the sidewalls of drift region. One can choose to have a higher blocking voltage or increase the background doping. A PiN structure, essentially identical to MOSFET during off state, was fabricated to demonstrate the proposed concept. Its measured BV/sub dss/ of 170 V is 2.5 times higher than measured conventional device BV/sub dss/ of 67 V on the same silicon wafer.

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization

The device physics of the double-gate tunneling field-effect transistor (DG TFET) is explored through two dimensional device simulations. The on-state drain current Ion of the DG TFET, which is based on band-to-band tunneling, has a strong dependence on the silicon film thickness TSi and the physics governing it is detailed. It is established that band-to-band tunneling at the surface is very strong and accounts for a large part of the total drain current. However, a substantial part of the total drain current Ids is contributed by a subsurface portion of the silicon film. Detailed potential distributions show that the coupling of two gate electrodes in the DG TFET could effectively reduce the tunneling width ωT at the center of the silicon film up to an optimum TSi where maximum drain current is obtained.

Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction

The device physics and guiding principles for the design of the double-gate tunneling field-effect transistor with silicon-germanium (SiGe) heterojunction source are discussed. Two dimensional device simulations were employed to study the influence of the position of the SiGe∕Si heterojunction on band-to-band tunneling and device performance. It is established that band-to-band tunneling occurs at a distance of ∼4nm from the gate edge in the source region. In order for the narrower bandgap of SiGe to play a dominant role, the overlap between the SiGe region and the gate should be such that the whole tunneling path of the electrons is located in SiGe. To harness the maximum benefits of the high band-to-band tunneling rate in SiGe, an overlap of ∼2nm between the SiGe region and the gate would be required.

Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

A novel double-gate (DG) tunneling field-effect transistor (TFET) with silicon–germanium (SiGe) Source is proposed to overcome the scaling limits of complementary metal–oxide–semiconductor (CMOS) technology and further extends Moores law. The narrower bandgap of the SiGe source helps to reduce the tunneling width and improves the subthreshold swing and on-state current. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. For the first time, we show that such a technology proves to be viable to replace CMOS for high performance, low standby power, and low power technologies through the end of the roadmap with extensive simulations.

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was found that tensile strain increases the drain current, whereas compressive strain reduces the drain current. This is attributed to strain-induced band splitting and carrier repopulation and provides guidelines on strain engineering of TFETs. An elaborate study of the dependence of the electrical characteristics of TFET on temperature is also reported. It was observed that on-state tunneling current exhibits a positive temperature dependence at low drain bias condition (V DS = 1 V), whereas opposite behavior was observed when V DS = 1.5 V. When the device temperature is increased, enhancement of the drain current at V DS = 1 V results from band gap narrowing, whereas reduction in the drain current at V DS = 1.5 V is attributed to the decrease in the electric field at the tunneling junction.