Kikuo Kusukawa

Single-pole/TMR heads for 140-gb/in/sup 2/ perpendicular recording

Single-pole writers and tunneling magnetoresistive (TMR) readers for 140-Gb/in/sup 2/ perpendicular recording were fabricated and their recording performance was tested. Data erasure, which is observed as write instability in a repeated read-write operation, can be suppressed by combining a laminated pole and low throat height. Fe-Co/Ni-Cr laminated film was used to reduce the remanent magnetization of the main pole after patterning. Narrow track writers with a 120-nm-wide trapezoidal pole showed a good write ability of 30 dB or more in overwrite for media with high coercivity of up to 7 kOe. Also, negligibly small skew writing was confirmed. TMR heads with a sensor width of 85 nm and a head resistance of 250 /spl Omega/ showed approximately 30 dB of head signal-to-noise ratio (SNR). A potentially higher SNR with a higher operating voltage was suggested from a measured output versus sensing current curve. Calculations showed that the side reading was suppressed in a side-shielded design. A 10% amplitude width of the microtrack profile of a 100-nm-wide reader was reduced from 198 to 162 nm by applying the side shields.

Low-temperature SOI (Si-on-insulator) formation by lateral solid-phase epitaxy

Low‐temperature (550–600 °C) formation of a Si‐on‐insulator structure by a solid‐phase process is investigated. A microprobe (μ) reflection high‐energy electron diffraction observation reveals that oriented crystal growth propagates from the seeding area in solid‐phase epitaxy (SPE). The effects of random nucleation, epitaxial alignment, and local doping on lateral (L)‐SPE are examined. As a result, a relatively large L‐SPE area, 14 μm from the seeding area, is achieved on insulating regions. Crystal quality and electrical properties of L‐SPE layers are examined using μ‐Raman spectroscopy and field‐effect transistor fabrication. A small stress field, 2.5×109 dyn/cm2, and high electron mobility, 720 cm2/V s, comparable to that of bulk Si are obtained.

Controlling the Solid-Phase Nucleation of Amorphous Si by Means of a Substrate Step Structure and Local Phosphorus Doping

We propose a solid-phase crystallization technique that controls the location of crystal grain formation on SiO2 substrates. This enables the formation of electronic devices in a single grain. To determine the condition of the technique, the nucleation characteristics of amorphous Si with P- and B-doping are investigated. Also, the characteristics with and without step structures on the substrate surface are reported and discussed. The various nucleation behaviors can be interpreted in terms of the critical size of the nucleus and of the rate of crystal growth.

Side-shielded tunneling magnetoresistive read head for high-density recording

To reduce the side-reading effect and obtain a narrower effective read track width, the side-shield effect was studied by computer simulations and experiments. Computer simulations show that the side shield, which consists of a soft magnet, can reduce the effective read track width. To examine the effect, a side-shielded tunneling magnetoresistive head was fabricated. In the head, to place a soft magnet by the sensor side, a closed-flux structure was applied for longitudinal bias instead of a conventional abutted junction. Microtrack profile measurements agreed with simulated results, and the side-shield effect was clearly demonstrated.

Influence of Si film thickness on growth enhancement in Si lateral solid phase epitaxy

Lateral solid phase epitaxial growth (L‐SPE) of Si on SiO2 film was investigated as a function of deposited amorphous Si (a‐Si) film thickness. Both the L‐SPE rate and the annealing time necessary for {111} facet formation increased with film thickness. As a result, a large L‐SPE length (9 μm) under {110} facet growth was obtained for a 1.6‐μm‐thick film sample. Above the critical film thickness (>2 μm), crack formation in a‐Si films was observed during deposition. This indicates that intrinsic stresses play an important role in this growth enhancement.

Enhancement of lateral solid phase epitaxy over SiO2 using a densified and thinned amorphous Si layer

Formation of a thin‐film silicon‐on‐insulator structure by lateral solid phase epitaxy of amorphous Si is described. Thinning of the amorphous Si layer after deposition and densification in an ultrahigh vacuum, prior to solid phase epitaxy, successfully enhances the lateral growth length. In addition, the crystallinity of thin silicon‐on‐insulator layers formed by this technique is found to be better than that achieved by the conventional method.

A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS)

A new three-dimensional one-transistor dynamic RAM cell is presented. It has a trench capacitor fabricated in the Si substrate. In addition, there is a switching transistor fabricated in a laser-induced SOI layer formed on top of the capacitor area. The cells advantages are a high capacitor capture ratio (capacitor area/cell area) and the capability of possessing high capacitance even when the cell size is reduced to less than 5µm2.

Seed shape dependence of Si solid-phase epitaxy: preferential facet growth

A new facet formation mode in Si lateral solid‐phase epitaxy (L‐SPE) of amorphous Si on SiO2 is presented. This mode occurs in the case of L‐SPE using a two‐dimensional seed area. Depending on whether the seed shape is convex or concave, a {111} facet with a slow SPE rate or a {110} facet with a fast SPE rate dominates in the case of {100} Si substrate. This preferential facet growth is explained using a microscopic model of crystallization, and seems to be generalized to other crystal growth and etching processes. Similar results are obtained for seeds surrounded by an SiO2 layer and for seeds surrounding an SiO2 island. These results must be considered in practical device design.

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabrication

A simple method for suppressing lateral diffusion of impurities during liquid-phase seeded lateral epitaxy is demonstrated. An undoped epitaxial Si layer selectively grown on the seeding region is used as a diffusion stopper. The source-to-drain electrical short observed in the MOSFETs fabricated in the vicinity of the doped seeding region is reduced by adopting the method. The method is also successfully applied to the fabrication of a three-dimensional DRAM cell stacked switching transistor in SOI, of (SSS) that includes a heavily doped seeding region in its structure. The cells are found to operate normally, in spite of the heavily doped region, owing to the diffusion suppression effect. >

Grown‐facet‐dependent characteristics of silicon‐on‐insulator by lateral solid phase epitaxy

Electrical characteristics of Si layers on SiO2 formed by seeded lateral solid phase epitaxy are evaluated using metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) fabricated in the layer. To evaluate the {110} and {111} facet grown areas separately, the locations of the MOSFET’s are varied as a function of distance from the seeding region. Significant differences in electrical characteristics of the MOSFET’s are observed depending on the single‐crystal growth mode. A field‐effect (electron) mobility of about 700 cm2/(V s) was obtained for n‐channel MOSFET’s fabricated in the {110} facet grown region. That for the {111} facet growth region was inadequate. The results indicate the possibility of applying the method for future three‐dimensional device structures using a {110} facet grown region.