Makoto Ohkura

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.

12.4: Late-News Paper: Selectively Enlarging Laser Crystallization Technology for High and Uniform Performance Poly-Si TFTs

A novel method for laser-recrystallized poly-Si layer formation is proposed. The pulse-duration-controlled solid-state laser is utilized to enhance the lateral crystal growth, and an excimer- laser-crystallized poly-Si layer is used as a precursor. The validity of the method is confirmed by superior TFT characteristics of high field-effect mobility (n-ch TIT:μ > 460 cm2/Vs, p-ch TFT: μ > 150 cm2/Vs) with low threshold voltage deviation (Vth: 3 σ < 0.25 V).

Process and device technologies for 1 Gbit dynamic random‐access memory cells

This article discusses the technological issues involved with continuing the miniaturization of dynamic random‐access memory cells into the gigabit era. Ever‐smaller giga‐generation dynamic random‐access memory cells require three‐dimensional high‐charge density capacitors with high‐e insulating films, leading to the need for further improvements in lithographic resolution for ever‐smaller, higher aspect ratio memory cells, and planarization technologies for reducing the memory‐cell height. This article demonstrates two technologies for meeting these two requirements: high acceleration energy electron‐beam lithography and KrF excimer‐laser phase‐shift photolithography, and plate‐wiring merge technology. Metal–insulator–metal 1.6 nm Ta2O5 CROWN capacitors and single Si3N4 spacer OSELO isolation technology for an experimental 1 Gbit dynamic random‐access memory chip are also discussed.

A mechanism and a reduction technique for large reverse leakage current in p-n junctions

The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature dependence, and therefore cannot be explained by either generation-recombination current or diffusion current. It may be explained by the local Zener effect at local enhancement of the electric field around small precipitates in the depletion layer. Supposing a spherical precipitate, the electric field will be enhanced as much as 1.3 times for a SiO/sub 2/ precipitate and 3 times for a metal precipitate. The leakage features are explained by the electric field dependence and the temperature dependence of the local Zener probability. A new approach to reduce the local Zener probability by controlling the profile of the electric field is proposed, and the validity of the approach is confirmed by direct experiment and by improvement in the refresh operation of DRAM cells. >

Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs

Device degradation under ac stress in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed with the density of trap states, electron-emission time, and electron-trapping time as foci. LTPS TFTs are shown to incur greater deterioration of characteristics under ac stress than silicon-on-insulator TFTs. Characteristics are more rapidly worsened as the falling time (t/sub f/) of gate pulses becomes shorter in the range below 1 ms. In addition, the degradation produced by a given number of pulses increases with the duration of the low level of the gate pulse in the range up to 1 ms. These behaviors are due to the slow emission of trapped electrons. On the other hand, the device degradation is independent of the duration of the high level of the gate pulse because the electrons are trapped quickly (in less than 1 /spl mu/s) once the level on the gate becomes high. The U-shaped distribution of trap-state density within the energy gap largely determines the dependence of the ac stress degradation on t/sub f/, since trapped electrons for which the emission time is longer than t/sub f/ are not emitted within the period of transient variation of gate voltage, and the number of electrons emitted after the gate has gone low increases with decreasing t/sub f/. Severe degradation is induced by ac stress conditions that correspond to electron emission from the trap states close to conduction band when the TFT is turned off.

Controlling the Solid-Phase Nucleation of Amorphous Si by Means of a Substrate Step Structure and Local Phosphorus Doping

We propose a solid-phase crystallization technique that controls the location of crystal grain formation on SiO2 substrates. This enables the formation of electronic devices in a single grain. To determine the condition of the technique, the nucleation characteristics of amorphous Si with P- and B-doping are investigated. Also, the characteristics with and without step structures on the substrate surface are reported and discussed. The various nucleation behaviors can be interpreted in terms of the critical size of the nucleus and of the rate of crystal growth.

Metal‐oxide‐semiconductor field‐effect transistors fabricated in laterally seeded epitaxial Si layers on SiO2

Metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) were fabricated in laterally seeded epitaxial Si layers on SiO2, using cw Ar laser irradiation. FET’s were distributed in various regions of the epitaxial films grown on SiO2, as well as directly on a Si substrate. Electronic properties were found to be good when compared with that for bulk Si, even though mobility at the SiO2 edge was somewhat poor. The results are discussed in connection with the crystal qualities examined through use of optical and electron microscopy.

Enhancement of lateral solid phase epitaxy over SiO2 using a densified and thinned amorphous Si layer

Formation of a thin‐film silicon‐on‐insulator structure by lateral solid phase epitaxy of amorphous Si is described. Thinning of the amorphous Si layer after deposition and densification in an ultrahigh vacuum, prior to solid phase epitaxy, successfully enhances the lateral growth length. In addition, the crystallinity of thin silicon‐on‐insulator layers formed by this technique is found to be better than that achieved by the conventional method.

A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS)

A new three-dimensional one-transistor dynamic RAM cell is presented. It has a trench capacitor fabricated in the Si substrate. In addition, there is a switching transistor fabricated in a laser-induced SOI layer formed on top of the capacitor area. The cells advantages are a high capacitor capture ratio (capacitor area/cell area) and the capability of possessing high capacitance even when the cell size is reduced to less than 5µm2.