Kimihiro Yamanaka

Materials, Processes, and Performance of High-Wiring Density Buildup Substrate With Ultralow-Coefficient of Thermal Expansion

Flip-chip bonding on organic sequential buildup substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance, there has been a rapidly increasing need for a finer pitch area array of flip-chip joints. However, the pitch has been limited by packaging technology. An advanced buildup substrate for fine pitch flip-chip bonding has been developed to satisfy the requirements for the most advanced semiconductor devices. The advanced substrate features a low-coefficient of thermal expansion (CTE) of 3 ppm°C, a fine pattern of 8 μm in line width and spacing, micro-vias of 25 μm in diameter, and plated through-holes of 100 μm in pitch. These features accommodate the density of a chip I/O of 104 cm-2, which is about ten times greater than that achieved in current organic packaging, and enable significant size reduction of semiconductor chips and the associated packages. The low-CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. This paper describes recent progress in the development of the advanced substrate technology as well as the technical difficulties.

Advanced Surface Laminar Circuit Packaging with low Coefficient of Thermal Expansion and high wiring density

Flip-chip bonding on organic sequential build-up substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance there has been a rapid increasing need for a finer pitch area array flip-chip joints. However, the pitch has been limited by the packaging technology. Advanced Surface Laminar Circuit (Adv-SLC) packaging technology has been developed to satisfy the requirements for the most advanced semiconductor devices. Adv-SLC is a build-up substrate featuring a low Coefficient of Thermal Expansion (CTE) of 3 ppm/°C, a fine pattern of 8 µm in line width and spacing, plated through-holes of 100 µm in pitch and micro-vias of 25 °m in diameter. These features accommodate the density of a chip I/O of 104 cm−2, which is about ten times greater than that achieved in current organic packaging, and enables significant size reduction of semiconductor chips and the associated packages. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. The CTE can be expanded to 5 ppm/°C by adjusting the volume ratio of the resin in the core. This paper describes recent progress in the development of Adv-SLC packaging technology.

Advanced Surface Laminar Circuit using new composite materials

This paper introduces a newly developed Advanced Surface Laminar Circuit (Adv-SLC) packaging technology, which utilizes new composite materials. Adv-SLC is a buildup substrate technology designed to satisfy the requirements of the most advanced semiconductor chips. We have developed a new dielectric material that is a build-up layer composed of two different materials. We also used a new material for the core substrate composed of Liquid Crystalline Polymer (LCP) reinforced with glass cloth. The new build-up layer has the following reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10μm and a via diameter of 30μm. The new core substrate also has excellent reliable properties as follows: it can maintain both conductivity and dielectricity under the condition of both a through hole diameter of 60μm and a through hole pitch of 120μm. We were able to confirm that the formation of the new substrate with the aforementioned new design rules contributes to reduce the silicon chip size. Consequently, due to all of the aforementioned properties, Adv-SLC contributes to reduce thermal stress when we mount a flip chip.

Advanced Surface Laminar Circuits Using Newly Developed Resins

This paper introduces a newly developed advanced surface laminar circuit (Adv-SLC) packaging technology, which utilizes new composite materials. Adv-SLC is a build-up substrate technology designed to fulfill the requirements of the most advanced semiconductor chips. Our new dielectric material is a build-up layer composed of two different materials. We also used a new material for the core substrate, composed of liquid crystalline polymer reinforced with glass cloth. The build-up layer has the following, highly reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10 μm and a via diameter of 30 μm . The core substrate also has excellent, reliable properties: it can maintain both conductivity and dielectricity under the conditions of a through hole diameter of 60 μm and a through hole pitch of 120 μm. We were able to confirm that the formation of the new substrate with the aforementioned new design rules contributes to reduce the size of the silicon chip. Consequently, Adv-SLC contributes to reduce thermal stress when mounting a flip chip.

Effects of the crystallographic orientation of Sn grain during electromigration test

The relationship between electromigration behavior and the crystallographic orientation of Sn grains was investigated. The test vehicle was the Cu/Sn−3.0wt%Ag−0.5wt%Cu/Cu dummy flip-chip model, and the applied current density was 15 kA/cm2 at 160 °C. The depletion of Cu atoms at the cathode side is a major cause of the early circuit failure. Electromigration behavior and the growth of intermetallic compounds were strongly depend on the orientation of Sn grains with respect to the electron flow. Rapid failure occurred when the c axis of Sn grains close to the parallel to the direction of the electron flow, due to the Cu depletion at the cathode side. Slight microstructural changes and improved electromigration properties were observed when the c axis of the Sn grains close to perpendicular to the direction of electron flow.

Interface Formation Between Metal and Polyimide in High Wiring Density Build-up Substrate

A key to a high-wiring-density build-up substrate is fine circuitry formation technology to satisfy the ever-increasing demands for miniaturization of electronics products. The surface roughness of a dielectric layer needs to be in the submicrometer scale for fine circuitry such as a line less than 10 μm wide. However, the Cu to dielectric adhesion strength of such a line would not be sufficient to prevent peeling off during manufacture and after heat treatment. Consequently, it is essential to have good adhesion between Cu and dielectric layer with chemical bonds between the metal and the dielectric layer. A polyimide film was introduced as a dielectric layer in a build-up substrate. Argon plasma-modified polyimide surfaces were sputtered with NiCr and then subjected to Cu electroplating. While unmodified polyimide had a weak adhesion strength of 0.12 kN m-1, Ar plasma-modified polyimide showed good adhesion strength of more than 0.5 kN m-1 even after 10 days of heat treatment at 172°C. X-ray photoelectron spectroscopy studies revealed that the adhesion strength was attributable to chemical bonds between Cr and the polyimide. Ar plasma-treated polyimide produced a large quantity of oxygen functional groups containing C=O bonds on the surface of polyimide, and subsequent NiCr sputtering produced C-O-Cr or C=O⋯Cr bonds to the polyimide. In addition, NiCr sputtering also attacked some of N-C=O and N-C bonds, and modified them to produce C-N-Cr or C-N⋯Cr bonds to the polyimide. These two types of mechanism produced sufficiently high Cu to polyimide adhesion to achieve fine line circuitry.

Effect of solders, underfills and substrates on the reliability of flip-chip bonding of low-k semiconductor chips

This study investigated the effect of solders, underfills and substrates on the reliability of a flip-chip package, focusing on the low-k layer in a semiconductor chip. After reflow, cracking and/or delamination were found in the low-k layer under the bump when Sn-2.5Ag solder was used. However, Indium solder did not induce cracking or delamination. Its softness mitigated the stress evolution in the low-k layer. After underfilling, cracking was observed at the chip edge during a −55/125 °C temperature shock test, when Indium was used with a higher glass transition temperature (Tg) underfill. Underfilling changed the maximum stress region to the chip edge from under the bump. However, when a low Tg underfill was used, no failure was observed up to 5800 cycles. Indium with a low Tg underfill had an advantage to enhance reliability of the low-k layer.