Kiran Kumar Gunnam | Researchain

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IEEE Solid-state Circuits Magazine | 2016

Algorithms and VLSI Architectures for Low-Density Parity-Check Codes: Part 1-Low-Complexity Iterative Decoding

Kiran Kumar Gunnam; Joan Marc Catala Perez; Francisco Garcia-Herrero

This article is the first of a two-part tutorial about low-density parity-check (LDPC) codes. These codes have been firmly established as error-correction coding techniques for communication and storage channels.

IEEE Solid-state Circuits Magazine | 2017

Algorithms and vlsi architectures for low-density parity-check codes: part 2 - efficient coding architectures

Kiran Kumar Gunnam; Joan Marc Catala Perez; Francisco Garcia-Herrero

This article is the second of a two-part tutorial about low-density parity-check (LDPC) codes. (The first part appeared in the Fall 2016 issue.) Here, we describe the min-sum decoding algorithm and explain the very-largescale integration (VLSI) architectures for nonlayered and layered decoders and the techniques to reduce memory and logic requirements in their implementations, pointing out the advantages and disadvantages of each.

Archive | 2017