Zvonimir Z. Bandic

Repair-optimal MDS array codes over GF(2)

Maximum-distance separable (MDS) array codes with high rate and an optimal repair property were introduced recently. These codes could be applied in distributed storage systems, where they minimize the communication and disk access required for the recovery of failed nodes. However, the encoding and decoding algorithms of the proposed codes use arithmetic over finite fields of order greater than 2, which could result in a complex implementation. In this work, we present a construction of 2-parity MDS array codes, that allow for optimal repair of a failed information node using XOR operations only. The reduction of the field order is achieved by allowing more parity bits to be updated when a single information bit is being changed by the user.

Coding scheme for 3D vertical flash memory

Recently introduced 3D vertical flash memory is expected to be a disruptive technology since it overcomes scaling challenges of conventional 2D planar flash memory by stacking up cells in the vertical direction. However, 3D vertical flash memory suffers from a new problem known as fast detrapping, which is a rapid charge loss problem. In this paper, we propose a scheme to compensate the effect of fast detrapping by intentional inter-cell interference (ICI). In order to properly control the intentional ICI, our scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. This technique is closely connected to the well-known problem of coding in a memory with defective cells. Numerical results show that the proposed scheme can effectively address the problem of fast detrapping.

Joint Source-Channel Decoding of Polar Codes for Language-Based Sources

We propose a joint list decoder and language decoder that exploits the redundancy of language- based sources during polar decoding. By judging the validity of decoded words in the decoded sequence with the help of a dictionary, the polar list decoder constantly detects erroneous paths after the decoding of every few bits. This path-pruning technique based on joint decoding has advantages over stand-alone polar list decoding in that most decoding errors in early stages are corrected. We show that if the language structure can be modeled as erasure correcting outer block codes, the rate of inner polar code can be increased while still guaranteeing a vanishing probability of error. To facilitate practical joint decoding, we first propose a construction of a dynamic dictionary using a trie and show an efficient way to trace the dictionary during decoding. Then we propose a joint decoding scheme for polar codes taking into account both information from the channel and the source. The proposed scheme has the same decoding complexity as the list decoding of polar codes. A list-size adaptive joint decoding is further implemented to largely reduce the decoding complexity. Simulation results show that the joint decoding schemes outperform stand-alone polar codes with CRC-aided successive cancellation list decoding by over 0.6 dB.

Locally rewritable codes for resistive memories

We propose locally rewritable codes (LWC) for resistive memories inspired by locally repairable codes (LRC) for distributed storage systems. Small values of repair locality of LRC enable fast repair of a single failed node since the lost data in the failed node can be recovered by accessing only a small fraction of other nodes. By using rewriting locality, LWC can improve endurance and power consumption which are major challenges for resistive memories. We point out the duality between LRC and LWC, which indicates that existing construction methods of LRC can be applied to construct LWC.

Balanced codes for data retention of multi-level flash memories with fast page read

Flash memories use the amount of charge (e.g., electrons) trapped in floating gate transistors to represent data. Charge leakage will cause data retention problem by unidirectionally shifting the cell-level distribution. Balanced codes are an effective means to adjust read thresholds adaptively and tolerate the charge leakage under unknown retention environments. For multi-level cell (MLC) flash memories with 4 levels, 2 binary logical pages are mapped to one quaternary physical page. In order to achieve a small read latency, one (or two, respectively) read threshold(s) is (are) applied to the physical page to retrieve data for the least significant bits (LSBs) (or most significant bits (MSBs), respectively). In this paper, we propose two coding schemes that use balanced codes for multi-level flash memories, which tolerate charge leakage and provide fast page read simultaneously. We prove that our coding schemes asymptotically bring no rate penalty (2 bits/cell for quaternary cells). We establish a model of the programming, retention, and read for MLC, then theoretically calculate the raw bit-error-rate (RBER) and page-error-rate (PER), and compare the performance of read threshold adjustments based on balanced codes and the conventional scheme that estimates the cell level drift. It is shown that for a fixed PER, the requirement for error correction codes (ECCs) when using balanced codes is much less than that of using conventional schemes, which has the benefits of ECC rates, decoding delay, and decoding complexity.

Latency Tails of Byte-Addressable Non-Volatile Memories in Systems

Next generation non-volatile memories, like Resistive RAM, Spin-Transfer Torque Magnetic RAM and Phase Change Memory, are byte- addressable with very low latency, bridging the large performance gap between DRAM memory and NAND flash storage. For this reason we think of them as Storage Class Memories (SCMs), meaning their main use could ideally be as main memory but the non-volatility and high density could also fill some of the needs for durable storage. The path to using SCMs as main memory will necessitate significant changes to prevailing CPU architectures, so at first our focus was on enabling their early market adoption as ultrafast storage in commodity systems. In stark contrast to NAND flash, whose read latency of a tenth of a millisecond dominates the total system response latency to a storage request, SCM-based devices are so fast that attach interface and host device driver latencies, which are in the microsecond domain, start to dominate the total response latency, hindering greatly the performance of SCMs in commodity systems. Moreover, the latency jitter introduced by host hardware and software and by controller firmware further affects the Quality of Service (QoS) of solid-state drives based on SCMs. In this paper we discuss various factors that degrade the QoS, including host software and machine configurations. A particular fine- tuning of an x86 host machine, a well-designed device driver and a low latency device controller result in an ultra-low latency system with excellent QoS. We measure less than 4 μs latency for 99.999% of I/O requests at queue depth one, and less than 7 μs at queue depth 32, from an SCM-based block device on PCI Express interface.

Locally Rewritable Codes for Resistive Memories

Resistive memories, such as phase change memories and resistive random access memories, have attracted significant research interest because of their scalability, non-volatility, fast speed, and rewritability. However, their write endurance needs to be improved substantially for large-scale deployment of resistive memories. In addition, their write power consumption is much higher than the power consumption of read operation. Inspired by locally repairable codes (LRCs) recently introduced for distributed storage systems, we propose locally rewritable codes (LWCs) for resistive memories. We define a novel parameter of rewriting locality , which can be connected to repair locality of LRC. As small values of repair locality of LRC enable fast repair in distributed storage systems, small values of rewriting locality of LWC are able to reduce the problems of write endurance and write power consumption. We show how a small value of rewriting locality can improve write endurance and power consumption by deriving the upper bounds on writing cost. Also, we point out the dual relation of LRC and LWC, which indicates that the existing construction methods of LRC can be applied to construct LWC. Finally, we investigate the construction of LWC with error correcting capability for random errors.

Hardware accelerator for similarity based data dedupe

Data deduplication has proven important in backup storage systems as large amount of identical or similar data chunks exist. Recent studies have shown the great potential of data deduplication in primary storage and storage caches. Deduplications in these environments require high speed processing not to drag down production performance. This paper presents a hardware accelerator for similarity based data deduplication. It implements three compute-intensive kernel modules to improve throughput and latency in dedupe systems: sketch computation for data blocks, index searching for reference block, and delta encoding over similar blocks. Adopting pipelined computation and parallel data lookup across multiple hardware modules, our HW design is capable of processing high throughput data traffic by working on multiple data units concurrently, thus enabling wire speed dedupe for data stream where similar blocks present. Using a PC host system connected to the FPGA-based accelerator through a PCIe Gen 2×4 interface, our experiments show that the similarity based data dedupe performs 30% better in data reduction ratio than conventional dedupe techniques that look at identical blocks only. By comparing the hardware implementation with its software counterpart, the experimental results show that our preliminary FPGA implementation with maximum clock speed of 250MHz achieves at least 6 times improvement in latency over the software implementation running on state-of-art servers.