Ravi H. Motwani

Robust decoder architecture for multi-level flash memory storage channels

Multi-level-cell (MLC) flash memory comprises of cells which can be programmed to multiple levels. Recent MLC flash memory systems support 3 bits per cell to 4 bits per cell which means that the individual cells are programmed to 8 or 16 distinct levels respectively. MLC flash has higher raw bit error rate (rber) than the single bit per cell flash. This calls for the use of sophisticated error control coding (ECC) schemes like LDPC codes. The flash memory channel is usually modeled with level distributions having Gaussian probability density function. However, the Gaussian distribution is not a good fit for practical NAND channels. Even for the beginning of life of the flash memory device, this model has to be replaced by a more realistic model. With erases and re-writes, the channel towards the end of life of the device is far from Gaussian and floating-gate to floating-gate coupling and charge loss not only increases the raw bit error rate but causes the level distributions to become asymmetric. Given such channel impairments, if the LDPC decoder assumes Gaussian level distributions, its performance can degrade considerably. Hence, modifications are required in the decoding algorithm to cope up with the channel distortions. In order to keep the hardware costs within limits, simple schemes with minimal hardware increase are desirable to keep up the performance. In this paper, the flash channel degradations are first enlisted and then simple solutions are proposed which keep the performance in check as the flash memory transits from a channel with moderate impairments to the end of life condition, where the level distributions for the different levels are highly asymmetric.

Design of LDPC coding schemes for exploitation of bit error rate diversity across dies in NAND flash memory

LDPC codes have been proposed for Flash memories due to their capability to correct higher number of bit errors. Several mechanisms can lead to bit errors in Flash memories. An extensive list of these mechanisms as enlisted in [1] includes program disturb from tunneling, quantum level noise effects, erratic tunneling, SILC-related data retention and read disturb, and detrapping-induced retention. Each of these effects can be modeled as a random event with its own statistical behavior. Due to the process uncertainties in the lithography, the above mechanisms vary from die to die leading to variability in the raw bit error rate (BER) for different dies of the Flash memory. This has an immense impact on design of error correction coding (ECC) schemes which combat the BER to achieve a specified uncorrectable bit error rate (UBER) target. If conventional ECC techniques are used, they have to be designed to handle the worst die BER, which is a big overkill. We propose a new LDPC coding scheme which exploits the BER diversity to its advantage and enables a system design for the average BER of the dies. The method is based on spreading the LDPC codeword over dies rather than packing a single LDPC codeword in one die. The system has to properly select the dies between which to split the LDPC codeword. The LDPC decoding has to be modified to account for the BER diversity. Simulations results show a large coding gain resulting from spreading a codeword, with minimal quality of service (QoS) impact. The improvement stems from the fact that the codeword splitting reduces the mean and the variance of the BER distribution. We also propose an LDPC code design which is customized to the codeword split across multiple dies. The proposed LDPC code design is on similar lines to its design for quasi-static fading channel. The LDPC code can be designed using density evolution to obtain an optimal degree distribution for a given BER distribution. Simulation results for the custom-designed LDPC codes validate the hypothesis by showing appreciable coding gains.

Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory

Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) can store more than one bit per cell. An ideal programming of a cell consists of injecting just the correct amount of charge in the cell by hot-electron injection. However, due to programming time constraints, some tolerance is accepted and the actual programming voltage is allowed to be within some range of the ideal. While programming a cell, due to the capacitive coupling between neighboring cells, the neighboring cells also get some charge. This phenomenon called as inter-cell-interference (ICI) can be from mild to extreme. Particularly, a cell at the lowest voltage level will pick up a lot of charge if its neighbors are then programmed to the highest level. In order to combat the noise due to ICI, constrained coding is a possible solution. Constrained coding consists of not allowing certain level patterns so that effects of ICI are contained. Constrained coding for solutions which have level information available while decoding all pages has been implemented for flash memory [1]. However, due to read latency requirements, level information may not be available while reading all pages and hence these codes cannot be used. We propose constrained codes which do not need level information while decoding all pages and hence average read latency requirements are met. Error propagation is a crucial degrading factor for constrained decoding and the codes we design are robust to channel noise. A new decoding algorithm which keeps synchronization which is crucial to contain error propagation is also proposed.

Construction of Random Input-Output Codes With Moderate Block Lengths

Random I/O (RIO) codes , recently introduced by Sharon and Alrod, is a coding scheme to improve the random input/output performance of flash memories. Multilevel flash memories require, on the average, more than a single read threshold in order to read a single logical page . This number is important to be optimized since it sets the read latency of flash memories. An

Construction of random input-output codes with moderate block lengths

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Soft decision decoding of RAID stripe for higher endurance of flash memory based solid state drives

RIO code assumes that

Estimation of Flash Memory Level Distributions Using Interpolation Techniques for Optimizing the Read Reference

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Guest Editorial Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems

pages are stored in

Signal processing techniques for ensuring fidelity of back-end signal transmission in flash memory based solid state drives

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Defect management policies for nand flash memory

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