Mase J. Taub

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.

A 172mm 2 32Gb MLC NAND flash memory in 34nm CMOS

As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements [1,2]. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device that employs chip architecture, datapath, and analog architecture solutions that address these challenges while meeting high performance requirements. This 32Gb MLC NAND delivers 50µs tREAD, 900µs tPROG and 9MB/s write throughput in a 34nm technology.