Kiryong Song

D-Band Heterodyne Integrated Imager in a 65-nm CMOS Technology

A D-band heterodyne integrated imager, consisting of a mixer, an oscillator, an IF amplifier, and an IF detector, has been developed in a 65-nm CMOS technology. A measured responsivity of 720 kV/W and noise equivalent power (NEP) of 0.9 pW/Hz1/2 were obtained at 125 GHz. A total dc power of 74 mW was dissipated. The chip size is 1200×800 μm2 including contact pads and an input balun. A D-band image was acquired with the imager serving as a detector. A significant resolution enhancement was demonstrated with a near-field imaging achieved by a metal plate with a pinhole in the imaging setup.

Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm2 (PLL1) and 1300 × 840 μm2 (PLL2) including probing pads.

An overview of challenges and current status of Si-based terahertz monolithic integrated circuits

Challenges in the implementation of THz circuits based on Si-based technologies such as Si CMOS and SiGe HBT technologies are overviewed in this paper. Major challenges described in this work include the operation speed of Si devices, loss of Si substrate, model accuracy, uncertainty in EM simulation, and the presence of dummy patterns. Possible techniques to partly circumvent the challenges are also discussed. A review of recently reported Si-based circuits operating beyond 100 GHz is provided.

A CMOS 300-GHz 7 by 7 detector array for THz imaging

In this work, a 300-GHz 7×7 imaging detector array has been developed with a 65-nm CMOS technology. Each pixel is made of an identical 300-GHz common-gate differential direct detector integrated with a patch antenna. The detector exhibits a 1,200 V/W responsivity and a 20 pW/Hz05 NEP by simulation. The fabricated chip area is 4×4 mm2 including wire-bonding pads. Employing the fabricated 7×7 detector array as a detector, real-time reflection imaging at 300 GHz was successfully carried out.

Approaches to enhance the performance of SiGe imagers operating near 130 GHz and 300 GHz

A comparison is made on high-frequency SiGe imagers to investigate the performance enhancement with circuit-level approaches: employing a front-end low noise amplifier (LNA) and employing heterodyne topology. Two imagers operating near 130 GHz, one with and the other without an LNA, were compared for the responsivity and the noise equivalent power (NEP). Also, two imagers operating near 300 GHz, one in direct and the other in heterodyne topology, were compared for the same parameters. Inserting a front-end LNA has led to changes in the peak responsivity and the minimum NEP with a factor of 63.5 and 0.011, respectively, near 130 GHz. Employing heterodyne topology for the 300 GHz imager resulted in changes with a factor of 52.8 and 0.18 for the same parameters.

An oscillator and a mixer for 140-GHz heterodyne receiver front-end based on SIGe HBT technology

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 ㎓ based on SiGe HBT technology. Firstly, a 123-㎓ oscillator was developed based on Colpitts topology, which showed - 5 ㏈m output power and phase noise of -107.34 ㏈c/㎐ at 10 ㎒. DC power dissipation was 25.6 ㎽. Secondly, a 135 ㎓ mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 ㏈ at 1 ㎓ IF at fixed LO frequency of 134 ㎓. DC power dissipation was 3 ㎽, which mostly comes from the buffer.

D-band Stacked Amplifiers based on SiGe BiCMOS Technology

This paper presents two 3-stage D-band stacked amplifiers developed in a 0.13-μm SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.