Namhyung Kim

A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².

A 248–262 GHz InP HBT VCO with Interesting Tuning Behavior

A fundamental-mode common-base voltage-controlled oscillator (VCO) based on 250-nm InP heterojunction bipolar transistor (HBT) technology is reported. The VCO, which employs varactors implemented by connecting the base and emitter of npn transistors as tuning components, shows a tuning range of 247.8-262.2 GHz. The output power is greater than 0 dBm over the entire tuning range, and dissipated dc power is around 85 mW. An unexpected tuning behavior was observed, which was shown to arise from the internal parasitic base inductance of the transistors used for varactors in this work.

A 47 GHz

A 47 GHz LC cross-coupled voltage controlled oscillator (VCO) employing the high-Q island-gate varactor (IGV) based on a 0.13 ¿m RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With VDD of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of -95.4 dBc/Hz and -91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-Q IGV. The VCO with IGV exhibited an output power of around -15 dBm, leading to a FoM of -182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).

LC

A D-band heterodyne integrated imager, consisting of a mixer, an oscillator, an IF amplifier, and an IF detector, has been developed in a 65-nm CMOS technology. A measured responsivity of 720 kV/W and noise equivalent power (NEP) of 0.9 pW/Hz1/2 were obtained at 125 GHz. A total dc power of 74 mW was dissipated. The chip size is 1200×800 μm2 including contact pads and an input balun. A D-band image was acquired with the imager serving as a detector. A significant resolution enhancement was demonstrated with a near-field imaging achieved by a metal plate with a pinhole in the imaging setup.

Cross-Coupled VCO Employing High-

Recently, the demand on ㎜-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the ㎜-wave frequency band have been traditionally implemented in Ⅲ-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled ㎜-wave circuits realized in a Si CMOS technology. In this work, a 58 ㎓ CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a 0.13-㎛ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the ㎜-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 ㎓ with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 ㏈c/㎐ at 5 ㎒ offset was achieved. The output power varied around -20 ㏈m over the measured tuning range. The circuit drew current (including buffer current) of 10 ㎃ from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 ㏈c/㎐.

Q

Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 × 760 μm2 (PLL1) and 1300 × 840 μm2 (PLL2) including probing pads.

Island-Gate Varactor for Phase Noise Reduction

In this paper, a receiver has been developed in a CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as . The chip size is excluding the probing pads.

D-Band Heterodyne Integrated Imager in a 65-nm CMOS Technology

Challenges in the implementation of THz circuits based on Si-based technologies such as Si CMOS and SiGe HBT technologies are overviewed in this paper. Major challenges described in this work include the operation speed of Si devices, loss of Si substrate, model accuracy, uncertainty in EM simulation, and the presence of dummy patterns. Possible techniques to partly circumvent the challenges are also discussed. A review of recently reported Si-based circuits operating beyond 100 GHz is provided.

A Millimeter-Wave LC Cross-Coupled VCO for 60 GHz WP AN Application in a 0.13-μm Si RF CMOS Technology

A 130-GHz OOK transmitter has been developed based on a 65-nm CMOS technology in this work. The transmitter is composed of a 130-GHz fundamental oscillator and a switch-based OOK modulator. The oscillator is based on an LC cross-coupled differential pair with a tapered buffer, while the switch adopts a 3-stage shunt configuration. The on/off power ratio of the switch is over 20 dB, and the transmitter exhibits an output power of -5.1 dBm with the switch turned on. The 3-dB bandwidth of the transmitter measured with a frequency domain technique is 16 GHz. The transmitter consumes 55.2 mW, mostly arising from the oscillator.

Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

In this work, a 280-GHz VCO integrated with a frequency divider with a large division ratio is presented. The triple-push Colpitts VCO, fabricated in a 65-nm CMOS technology, showed a tuning range of 279.9-283.0 GHz (3.1 GHz). The divider chain consists of two injection-locked frequency dividers (ILFDs and twelve current-mode logic (CML) dividers With the total division ratio of 16,384, the divider chain successfully divided the fundamental frequency (f0) of the VCO down to near 5.8 MHz. Total DC power consumption of the entire circuit was 131 mW.