Kisho Ashida

Development of New Power MOSFETs Package With Double-Sided Cooling

We developed a new packaging technology, one that uses double-sided cooling to dramatically reduce the on-resistance and thermal resistance. The main features of this technology are as follows. Both sides of the chip are soldered to copper leadframes. After that, copper leadframes soldered to the top and bottom of the chip are exposed when transfer molding encapsulates the package. There were two development problems with packaging technology. The first is how to prevent chip crack in the reflow process. The second is how to improve the fatigue life of solder during the temperature cycling. To solve these problems, we designed our package structure using an experimental design method. In particular, for the second problem, we quantitatively calculated the amount of solder fatigue fracture and the number of cycles using the solder crack propagation analysis method, because the performance of the package depends on the amount of solder fatigue fracture. As a result, we could create a condition that prevented chip crack and improved the fatigue life of solder by the twice compared to the first prototype and determined the optimum structure. We assembled a new package based on this optimum structure, and confirmed this improvement of the reliability. In addition, we measured the on-resistance and thermal resistance of this package and that of the existing package available. We found that the new package’s on-resistance and thermal resistance decreased to about 70 and 80% that of the existing package respectively.Copyright