Kishore K. Muchherla

Modeling the Driver Load in the Presence of Process Variations

Feature sizes of less than 90 nm and clock frequencies higher than 3 GHz calls for fundamental changes in driver-load models. New driver-load models must consider the process variation impact of the manufacturing procedure, the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. The present deterministic driver-load models use the conventional deterministic driver-delay model with a single Ceff (one ramp) approach. Neither the statistical property of the driver nor the inductance effects of the interconnect are taken into consideration. Therefore, the accuracy of existing models is questionable. This paper introduces a new driver-load model that predicts the driver-delay changes in the presence of process variations and represents the interconnect load as a distributed resistance, inductance and capacitance (RLC) network. The employed orthogonal polynomial-based probabilistic collocation method (PCM) constructs a driver-delay analytical equation from the circuits output response. The obtained analytical equation is used to evaluate the driver output delay distribution. In addition, the load is modeled as a two-effective-capacitance in order to capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of the inductance when modeling the driving-point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error over the simulation program with integrated circuit emphasis (SPICE) and the one ramp modeling approaches. Compared with the Monte Carlo method, the proposed model demonstrates a less than 3% error in the expected gate delay value and a less 5% error in the gate delay variance

A New Three-Piece Driver Model with RLC Interconnect Load

The scaled down feature size and the increased frequency of todays deep sub-micron region call for fundamental changes in driver-load models. To be more specific, new driver-load models need to take into consideration the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. Current driver-load models use the conventional single Ceff (one-ramp) approach and treat the interconnect load as lumped RC networks. Neither the nonlinear property nor the inductance effects were considered. The accuracy of these existing models is therefore questionable. This paper introduces a new multi-ramp driver model that represents the interconnect load as a distributed RLC network. The employed two effective capacitance values capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of inductance when modeling the driving point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error compared to SPICE.

A noniterative equivalent waveform model for timing analysis in presence of crosstalk

In the deep sub micron (DSM) regime, due to non-uniform scaling of interconnects, coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. Crosstalk causes delay variations on signal lines and raises signal integrity problems. Including crosstalk in timing analysis has become imperative for current technologies. Existing timing analysis methods do not consider gate driving capability, output loading effects and waveform shape, and hence are not always accurate. We propose a non-iterative equivalent waveform model that addresses these issues.

A non-iterative equivalent waveform model for timing analysis in presence of crosstalk

In the deep sub micron (DSM) regime, due to non-uniform scaling of interconnects, coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. Crosstalk causes delay variations on signal lines and raises signal integrity problems. Including crosstalk in timing analysis has become imperative for current technologies. Existing timing analysis methods do not consider gate driving capability, output loading effects and waveform shape, and hence are not always accurate. We propose a non-iterative equivalent waveform model that addresses these issues.