Janet Meiling Wang

Stochastic analysis of interconnect performance in the presence of process variations

Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.

Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources

This paper presents a method for general reduced order analysis of linear circuits with a large number of independent sources. This type of circuit is used to model the power grid in power supply noise analysis for example. The large size of the linear circuit model renders circuit simulation inefficient. The large number of independent sources makes conventional multi-port model reduction ineffective. In order to address these problems, this paper proposes an extended Krylov subspace method which constructs a transformation matrix based on the dynamics of the circuit as well as the source excitations, thus avoiding the multi-port problem of model reduction. The transformation matrix is then used to reduce the given circuit to a smaller circuit model, which allows for more efficient analysis.

Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

Variations in the interconnect geometry of nanoscale ICs translate to variations in their performance. The resulting diminished accuracy in the estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g., moments, distribution, etc.) of the interconnects response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or as spatial random processes. The corner-based analysis is not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables. This study proposes an efficient method of computing the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by projecting the infinite series representation onto a finite dimensional subspace. The advantage of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called orthogonal polynomial expansions for response analysis (OPERA). Results from OPERA simulations on a number of design test cases match well with those from the classical Monte Carlo simulation program with integrated circuits emphasis (SPICE) and from perturbation methods. Additionally, OPERA shows good computational efficiency: speedup of up to two orders of magnitude have been observed over Monte Carlo SPICE simulations

On projection-based algorithms for model-order reduction of interconnects

Model-order reduction is a key technique to do fast simulation of interconnect networks. Among many model-order reduction algorithms, those based on projection methods work quite well. In this paper, we review the projection-based algorithms in two categories. The first one is the coefficient matching algorithms. We generalize the Krylov subspace method on moment matching at a single point, to multipoint moment-matching methods with matching points located anywhere in the closed right-hand side (RHS) of the complex plane, and we provide algorithms matching the coefficients of series expansion-based on orthonormal polynomials and generalized orthonormal basis functions in Hilbert and Hardy space. The second category belongs to the grammian-based algorithms, where we provide efficient algorithm for the computation of grammians and new approximate grammian-based approaches. We summarize some important properties of projection-based algorithms so that they may be used more flexibly.

HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

Stochastic Power Grid Analysis Considering Process Variations

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grids electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis.

A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.

Principle Hessian direction based parameter reduction with process variation

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a principle Hessian direction (PHD) based parameter reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis (PCA) method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.

NBTI aware workload balancing in multi-core systems

As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).

Passive model order reduction algorithrrl based on Chebyshev expansion of impulse response of interconnect networks

In this paper, we provide a new passive model order reduction algorithm on interconnects, which is based on the Chebyshev expansion of their impulse response. The Chebyshev coefficient matrices of the impulse response of the reduced order model up to a given order remain the same as those of the original network, so that the time domain transient response of the reduced order model matches that of the original network well. Compared with the model order reduction algorithms based on the frequency domain response, it is more efficient in dealing with complicated transient waveforms of interconnects where strong inductance effects are involved.