Toshinobu Kashiwabara

One-dimensional logic gate assignment and interval graphs

This paper gives a graph-theoretic approach to the design of one-dimensional logic gate arrays using MOS or I^{2}L units. The incidence relation between gates and nets is represented by a graph H=(V,E) , and a possible layout of gates and nets is characterized by an interval graph \hat{H} = (V, E \cup F) , where F is called an augmentation. It is shown that the number of tracks required for between-gate wiring is equal to the clique number (chromatic number) of H , and hence the optimum placement problem is converted to that of minimum clique number augmentation. This turns out to be an NP -complete problem. Instead a polynomial-time algorithm for finding a minimal augmentation is presented, where an augmentation is minimal if no proper subset of it is an augmentation. An algorithm for gate sequencing with respect to a given augmentation is also presented.

On optimum single-row routing

The problem of single-row routing represents the backbone of the problem of general routing of multilayer printed circuit boards. In this paper, the necessary and sufficient condition for optimum single-row routing is obtained. By optimum routing we mean minimumm street congestion. A novel formulation is introduced. Examples are given to illustrate how optimum routings are derived. A graph theory interpretation of the condition is also given.

Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction

One of important questions on quantum computing is whether there is a computational gap between the model that may use quantum effects and the model that may not. Researchers have shown that some quantum automaton models are more powerful than classical ones. As one of classical computational models, branching programs have been studied intensively as well as automaton models, and several types of branching programs are introduced including read-once branching programs and bounded-width branching programs. In this paper, we introduce a new quantum computational model, a quantum branching program, as an extension of a classical probabilistic branching program, and make comparison of the power of these two models. We show that, under a bounded-width restriction, ordered quantum branching programs can compute some function that ordered probabilistic branching programs cannot compute.

Efficient algorithms for finding maximum cliques of an overlap graph

Let F = {I1, I2,…,In} be a finite family of closed intervals on the real line. Two intervals Ij and Ik in F are said to overlap each other if they intersect but neither one of them contains the other. A graph G = (V, E) is called an overlap graph for F if there is a one-to-one correspondence between V and F such that two vertices in V are adjacent to each other if and only if the corresponding intervals in F overlap each other. In this paper, we present two efficient algorithms for finding maximum cliques of an overlap graph when it is given in the form of a family of n intervals. The first algorithm finds a maximum clique in O (n. log n + Min {m, n- ω}) time, where m is the number of edges and ω is the size of a maximum clique, respectively, of the graph. The second algorithm generates all maximum cliques in O (n - log n + m + γ) time, where γ is the total sum of their sizes.

Generation of maximum independent sets of a bipartite graph and maximum cliques of a circular-arc graph

We present an efficient algorithm for generating all maximum independent sets of a bipartite graph. Its time complexity is O(n2.5 + (output size)), where n is the number of vertices of a given graph. As its application, we develop an algorithm for generating all maximum cliques of a circular-arc graph. When the graph is given in the form of a family of n arcs on a circle, this algorithm runs in O(n3.5 + (output size)) time.

On minimal augmentation of a graph to obtain an interval graph

Abstract This paper deals with the problem of adding edges to a graph such that the resulting graph becomes an interval graph. The set of edges added is called an augmentation. An algorithm is presented to find a minimal augmentation which runs in a time proportional to the product of the number of vertices and the number of edges of the resulting graph.

Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs

This paper deals with verification of high-level designs, in particular, symbolic comparison of register-transfer-level descriptions and behavioral descriptions. As models of those descriptions, we use state machines extended by quantifier-free first-order logic with equality. Since the signals in the corresponding outputs of such descriptions rarely change simultaneously, we cannot adopt the classical notion of equivalence for state machines. This paper defines a new notion of consistency based on signal-transitions of the corresponding outputs, and proposes an algorithm for checking consistency of those descriptions, up to a limited number of steps from initial states. A simple hardware/software codesign is taken as an example of high-level designs. A C program for digital signal processing called PARCOR filter was compared with its corresponding design given as a register-transfer-level description, which is composed of a VLIW architecture and assembly code. Since this example terminates within approximately 4500 steps, symbolic exploration of a finite number of steps is sufficient to verify the descriptions. Our prototype verifier succeeded in the verification of this example in 31 minutes.

Polynomial time algorithms on circular-arc overlap graphs

Let S be a family of arcs on a circle. A graph G = (V,E) is called a circular-arc overlap graph for S if (i) there is a one-to-one correspondence between V and S and (ii) two vertices in V are adjacent if and only if the corresponding arcs in S intersect but neither one of them contains the other. In this article, we present two polynomial time algorithms on circular-arc overlap graphs. Given a circular-arc overlap graph in the form of a family of n arcs, the first algorithm obtains a maximum independent set in O(n2) time and the second one finds a maximum clique in O(n5) time.

Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints

For formal verification of large-scale digital circuits, a method using satisfiability checking of logic with equality and uninterpreted functions has been proposed. This logic, however, does not consider specific properties of functions or predicates at all, e.g. associative property of addition. In order to ease this problem, we introduce “equivalence constraint” that is a set of formulas representing the properties of functions and predicates, and check the satisfiability of formulas under the constraint. In this report, we show an algorithm for checking satisfiability with equivalence constraint and also experimental results.

Automatic monitor generation from regular expression based specifications for module interface verification

In order to verify module interfaces, various verification methods have been proposed. This paper focuses on monitor-based verification of module interfaces. Monitor circuits are usually described by hand. This is a very hard task, however, since it requires low-level design of circuits or state machines. If specifications of module interfaces are described in more a comprehensive way, and monitor circuits are generated by the description, we can verify module interfaces more efficiently. In our method, first, we describe specifications of module interfaces in a language based on regular expressions, then construct behavior models from the description. Finally, we generate a monitor circuit. The circuit connects to a verification target to check whether interface behaviors of the target satisfy the specification. If interface behaviors violate the specification, the circuit asserts an error signal. In this paper, we state the method, and show a verification example based on simulation in which FSM state coverage is monitored.