Kiyotaka Tsuji

A novel retina chip with simple wiring for edge extraction

A novel silicon retina chip based on the information processing in the vertebrate retina was designed and fabricated. The chip has a novel wiring structure in which all pixels are connected through the channel of MOS transistors, which simplifies a wiring structure compared with conventional resistive networks. The proposed structure minimizes the pixel area and certainly increases a fill factor since each pixel consists of only two photodiodes and three MOS transistors. Experimental results showed that the chip could extracted the edge of input images successfully. Furthermore, it was shown that the chip could operate over a wide range of light intensities by adjusting its spatial resolution.

An optical adaptive device and its application to a competitive learning circuit

A mechanism suppressing the divergence of synaptic weights should be added to the network performing unsupervised learning algorithms with the Hebbian rule. In order to realize competitive learning in hardware, a synaptic connection circuit keeping a sum of synaptic weights constant was fabricated with the complementary field effect transistor (CMOS) floating gate process. The synaptic weights of each neuron were varied by applying the optical correction signals. The sum of synaptic weights was kept constant and the weights were memorized in a nonvolatile manner. A primitive competitive learning circuit was constructed with the synaptic connection circuits and a winner-take-all (WTA) circuit. The self-organization of the competitive circuit was confirmed experimentally and by means of simulations. The limitation of operating range and the feasibility of large-scale integration were discussed.

Self-organizing network for feature-map formation: analog integrated circuit robust to device and circuit mismatch

Abstract A network model self-organizing a feature map was proposed and investigated in computer simulations as well as experiments. The network was quite effective for self-organizing a feature map, in which winner groups are formed with redundant neurons. Fundamental circuits for the self-organizing network were developed. The experimental results were in good agreement with results of SPICE simulation. It was verified in a primitive network that feature maps were self-organized with high probability for 9 input patterns. It was clarified that redundant neurons forming a winner group are a key for solving a problem of wrong operation in analog circuits caused by the device and circuit mismatch.

An Adaptive Silicon Retina Performing an Edge Extraction with a MOS-Type Spatial Wiring and Smart Pixel Circuits

The vertebrate retina is the earliest neuronal element which performs a smart vision-processing, such as photoinput sensing, motion detection and so on. Among the retinal functions, the edge extraction of input images is the most important feature since it is believed to be necessary for the aggregation processes of the neuronal information in the brain. Recently, several artificial retina chips using silicon integration technology have been proposed for implementing the edge extraction system[1]-[5]. In those chips, a spatial smoothing task of the input images, which is performed by the retinal horizontal cells, has been realized by a resistive network[1]. The network is composed of resistive circuits which are formed by passive resistors using several MOS transistors[1]-[3] or resistors of a diffusion layer[4]. In order to improve the filtering performance of the resistive network, the pixel should be connected with not only the nearest neighbor pixels but also the second neighbor pixels[5]. However, it is very hard to connect a pixel with the second neighbor pixels since those resistive networks require a complicated wiring structure and large chip area. Our proposed silicon retina chip simplifies the wiring between pixels. Each pixel is connected to all pixels with a variable conductance, which enables the chip to adapt to global light intensities.

Topological mapping formation in a neural network with variations of device characteristics

The neural network of a human brain can well perform higher-order-information processing which could not be achieved by Neuman-type computers. In order to perform the processing, it is necessary to fabricate artificial neural systems which can form the topological mapping through learning. A new learning algorithm and a new network model have been proposed for fabrication by means of CMOS analog circuits with variations of device characteristics. The functions of those circuits were confirmed by means of SPICE simulations and the functions of PDM (pulse density modulator) were confirmed experimentally. The learning simulations of the network consisting of the circuits have also been carried out. The results show that the topological mapping is almost formed, even when variations of device characteristics exist in the neural network. The results also reveal that calculating the weighted sum of each neurons potential and potentials of its surrounding neurons as the output of each neuron and adding proper number of redundant neurons to the output layer are effective mechanisms for the network with variations of device characteristics.

A novel optical adaptive neuro-device using a split-gate MOS transistor

An optical adaptive neuro-device in which a split-gate MOS transistor is used to generate and inject hot electrons is presented. The proposed adaptive neuro-device has been fabricated by a double poly Si n-channel MOS process, and its operation has been experimentally verified. It has also been successfully applied to a synaptic connection circuit keeping the sum of synaptic weights in a neuron constant with time. Since it occupies much less area than previous adaptive neuro-devices based on electron tunneling and possesses promising characteristics, this device may be suitable as a fundamental synaptic connection device for the hardware implementation of large-scale artificial neural networks.